Re: idt reset issue

All,
   I apologize for missing the call this morning. It turns out that
Thursday mornings are just too busy for me to attend.

I have updated the document to include an model that patterns the
desired behavior. You can find the updated version at
http://designers-guide.org/private/vams-extensions/idt-issue.pdf

Also, I would like to offer the use the my online forum for use by the
Verilog-AMS committee. We used it when defining the compact model
extensions and I found it to be a very convenient way to carrying on the
conversations about particular issues. It naturally separates the
discussion threads and makes them easy to follow. If you wanted to do
this, I would give you a private board, so only invitees would be
allowed to see the board or contribute.

-Ken


Geoffrey.Coram wrote:
> Resending for Ken Kundert; original message bounced (too long).
> Attachment has been saved as
> http://www.verilog.org/verilog-ams/htmlpages/public-docs/idt-issue.pdf
> 
> 
> ----------------- Original Message -------------
> All,
>     I'd like to join the meeting tomorrow and discuss the reset feature
> of the idt function. I have not had much luck using this feature through
> the years, and recently had a situation where I really needed it.
> Unfortunately, I found the Cadence implementation unsuitable once again,
> and when I dug in to it I found the LRM silent on critical aspects of
> this feature. I have attached a very short document that illustrates the
> issue and proposes what I believe to be the desirable behavior. If you
> all agree I will work on coming up with the needed modifications to the LRM.
> 
> -Ken