Re: idt reset issue

Ken,

I have performed this test with some other tools and they do not show the 
1.5 deltaT delay in picking up from a reset.

The current wording in section 4.4.5 of the proposed 2.3 LRM is:

        "When specified with initial conditions, idt() returns the value 
of the initial condition in
        DC and IC analyses or whenever assert is given and is non-zero. 
Without initial
        conditions, idt() multiplies its argument by infinity in DC 
analysis. Hence, without initial
        conditions, it can only be used in a system with feedback which 
forces its argument to
        zero (0)."

In the table 4.3 in section 4.4.5 some additional information is given:

        "Returns the time-integral of x from t0 to t with initial 
condition
        ic. assert is a integer-valued expression. idt returns ic when 
assert is non-zero. t0 is
        the time when assert last became 0. Where x is expr."

This wording is definitely ambiguous as even just returning ic whenever 
assert is non-zero and happily continuing where it left off before assert 
became non-zero would be acceptable according to this description!

Would the following wording be meet the demands?

        "Whenever assert becomes non-zero the lower bound of the 
time-integration is reset to the current time value."

To handle prolonged periods of assert being non-zero the word "becomes" 
may have to be changed to "is" so the time-integrator will start 
integrating from the moment the assert statement becomes zero.

Cheers,
Marq


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors









Ken Kundert <ken@designers-guide.com> 
Sent by:
owner-verilog-ams@server.eda.org
06-10-2006 00:24

To
VerilogAMS Reflector <verilog-ams@server.eda.org>
cc

Subject
Re: idt reset issue
Classification







All,
   I apologize for missing the call this morning. It turns out that
Thursday mornings are just too busy for me to attend.

I have updated the document to include an model that patterns the
desired behavior. You can find the updated version at
http://designers-guide.org/private/vams-extensions/idt-issue.pdf

Also, I would like to offer the use the my online forum for use by the
Verilog-AMS committee. We used it when defining the compact model
extensions and I found it to be a very convenient way to carrying on the
conversations about particular issues. It naturally separates the
discussion threads and makes them easy to follow. If you wanted to do
this, I would give you a private board, so only invitees would be
allowed to see the board or contribute.

-Ken


Geoffrey.Coram wrote:
> Resending for Ken Kundert; original message bounced (too long).
> Attachment has been saved as
> http://www.verilog.org/verilog-ams/htmlpages/public-docs/idt-issue.pdf
> 
> 
> ----------------- Original Message -------------
> All,
>     I'd like to join the meeting tomorrow and discuss the reset feature
> of the idt function. I have not had much luck using this feature through
> the years, and recently had a situation where I really needed it.
> Unfortunately, I found the Cadence implementation unsuitable once again,
> and when I dug in to it I found the LRM silent on critical aspects of
> this feature. I have attached a very short document that illustrates the
> issue and proposes what I believe to be the desirable behavior. If you
> all agree I will work on coming up with the needed modifications to the 
LRM.
> 
> -Ken
[attachment "ken.vcf" deleted by Marq Kole/EHV/RESEARCH/PHILIPS]