Verilog-AMS Committee Meeting Minutes - Oct 5 2006

Martin O'leary - Cadence
Graham Helwig - ASTC
Jim Barby - University of Waterloo
Patrick O'Halloran - Tiburon
Boris Troyanovsky, Tiburon
Marq Kole - NXP Semiconductors
David Miller - Freescale Semiconductor

Continued review of Chapter 4 - Expressions. Resumed from section 4.4.9.
The following corrections were noted.

Section 4.4.10 - The last sentence in the last paragraph should read:
"In AC small-signal analysis, the slew() function has unity transfer function."

Section 4.4.15 - Ensure that the different constant and dynamic arguments for above, cross, $limit, and timer are mentioned in the appropriate chapters.

Section 4.5.4.3 - Graham will check to ensure that vector parameters are allowed as the first argument to noise_table(), Also make a mention in this section that a vector can be a concatenation or vector parameter or combination of both, as long as the resulting "vector" is even in length (must be pairs).

Section 4.6.1 - Suggested to have a reference to the BNF similar to other sections. Try and reword the last two bullet points. What I want to say is that it can use locally defined variables, the input arguments, module level parameters and locally defined parameters. 

Section 4.6.2 - Section heading should be analog user defined function.

Section 4.6.2.3 - Formatting, keyword output should be bold. Also try and be consistent and ensure that inout and output arguments are connected to analog variable references, and not analog variable expressions.
Suggested to also have a negative example which shows that it is an error if you connect V(a) to an inout argument.

Section 4.6.3 - The last bullet point should indicate that you can call an analog user defined function from within an analog context, not just analog block. Analog context would then also allow you to call an analog UDF from within another analog UDF.

We need to clarify when editing the Mixed Signal chapter what happens if a user declares an analog parameter inside an analog named block which is assigned a constant digital UDF.

Also still unsure why we don't want to allow constant analog UDF's to be assigned as the parameter initialisation expression.  Seems that this sort of feature may be benificial to people that write Verilog-A only models. 

Mention an example of the dangers of the inout argument and how it is pass value in, pass value out, and **not** pass by reference.

Patrick asked if you can create a library of analog udf's (so declare them outside a module. This is not allowed, since digital doesn't allow it. One way to do it is to place them all in a file and then `include that file into each module that needs them.
System Verilog allows this by utilising the package declaration. Example can be found in Section 18.2 Packages of the SystemVerilog 3.1a LRM.


For next meeting, would like to go through some of the rework of Chapter 
4, in particular Section 4.2.1 where we needed to add in the math 
operators with the $ prefix, $sin, $cos, etc.
David to post the reworked document.

Next meeting scheduled for Date & Time: 12 Oct 2006, 7:00am Pacific
Call-In Details:
 USA Toll Free Number: 877-346-8823
 USA Toll Number: +1-203-320-0407 (for intl)
 Participant Passcode: 602538

Cheers...
Dave

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-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
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