Question regarding connecting individual elements of a vector port

Hi all,
Is it perfectly valid to have a vector node where some of the elements 
are connected to ports and others are used as internal nodes? I can't 
see anything that explicitly restricts it from a syntax point of view, 
but was wondering if we should disallow it, or leave it intentionally 
ambiguous so that it is up to individual implementations?
The situation I am referring to is this below.

module blackbox(in[0]);
    electrical [0:1] in;
    analog begin
       V(in[0]) <+ 5;
       V(in[1]) <+ 10;
    end
endmodule

Here I have two constant voltage sources, where in[0] is used in a port 
connection, and in[1] is just a local source. Should this be allowed?

Dave

-- 
=====================================
-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
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