Re: Question regarding connecting individual elements of a vector port

Dave, Jon,

There is a mistake in the Verilog-A code: the vector range should not be 
present in the module port list, but can only be added in the port 
declaration itself -- the code below reflects that. Here is a clear syntax 
violation as you cannot declare a vector of just one element.

module blackbox(in);
    inout [0] in;
    electrical [0:1] in;
    analog begin
       V(in[0]) <+ 5;
       V(in[1]) <+ 10;
    end
endmodule

Also providing identical bounds does not help as that again is a violation 
of the range semantics:

module blackbox(in);
    inout [0:0] in;
    electrical [0:1] in;
    analog begin
       V(in[0]) <+ 5;
       V(in[1]) <+ 10;
    end
endmodule

However, if the module used two ports of the port vector on its interface, 
the current language definition would actually allow it.

module blackbox(in);
    inout [0:1] in;
    electrical [0:3] in;
    analog begin
       V(in[0]) <+ 5;
       V(in[1]) <+ 10;
       V(in[2]) <+ 5;
       V(in[3]) <+ 10;
    end
endmodule

Anyway, our compiler chokes on this telling me that it has a "conflict 
setting bounds for net 'in'". Interesting experiment, though :-)

Marq


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors









Jonathan David <j.david@ieee.org> 
Sent by:
owner-verilog-ams@server.eda.org
24-10-2006 22:32

To
Dave Miller <David.L.Miller@freescale.com>
cc
verilog-ams@server.eda.org
Subject
Re: Question regarding connecting individual elements of a vector port
Classification







I wouldn't think so, BUT.. is anything like this ever done (and allowed) 
in the digital Verilog world?
I would use that principle .. if the digital guys already do this  then 
its ok.. If they don't we shouldn't either
jbd
 
Jonathan David
j.david@ieee.org
jb_david@yahoo.com
http://ieee-jbdavid.blogspot.com
Mobile 408 390 2425
Work:
jbdavid@scintera.com
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408 200-7024

----- Original Message ----
From: Dave Miller <David.L.Miller@freescale.com>
To: Verilog-AMS LRM Committee <verilog-ams@eda.org>
Sent: Tuesday, October 24, 2006 11:13:20 AM
Subject: Question regarding connecting individual elements of a vector 
port

Hi all,
Is it perfectly valid to have a vector node where some of the elements 
are connected to ports and others are used as internal nodes? I can't 
see anything that explicitly restricts it from a syntax point of view, 
but was wondering if we should disallow it, or leave it intentionally 
ambiguous so that it is up to individual implementations?
The situation I am referring to is this below.

module blackbox(in[0]);
    electrical [0:1] in;
    analog begin
       V(in[0]) <+ 5;
       V(in[1]) <+ 10;
    end
endmodule

Here I have two constant voltage sources, where in[0] is used in a port 
connection, and in[1] is just a local source. Should this be allowed?

Dave

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