RE: Question regarding connecting individual elements of a vector port

I should point out that in the digital world, while it is legal, it is
discouraged. It is usually preferred to bring out the entire vector to
the port and to connect only those bits that you need.

 

Shalom

 

________________________________

From: owner-verilog-ams@server.eda.org
[mailto:owner-verilog-ams@server.eda.org] On Behalf Of Marq Kole
Sent: Thursday, October 26, 2006 1:41 PM
To: verilog-ams@server.eda.org
Subject: RE: Question regarding connecting individual elements of a
vector port

 


Dave, Jon, 

It looks like it can be done, and that the digital guys do it as well.
As far as I can tell from the section 12 examples -- as forwarded by
Shalom -- the correct way to describe this situation would be: 

module blackbox(.a(in[0]));
   input a; 
    electrical [0:1] in;
   analog begin
      V(in[0]) <+ 5;
      V(in[1]) <+ 10;
   end
endmodule

Can I presume that this part of the syntax is also covered in the
updated LRM 2.3 syntax? 

Cheers, 
Marq 


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors









"Bresticker, Shalom" <shalom.bresticker@intel.com> 

Sent by: 
owner-verilog-ams@server.eda.org 

25-10-2006 11:30 

To

"Jonathan David" <j.david@ieee.org> 

cc

<verilog-ams@server.eda.org> 

Subject

RE: Question regarding connecting individual elements of a vector
port 

Classification

 

 

 

 




1364-2005 12.3.3 has the following examples:

module test(a,b,c,d,e,f,g,h);
input [7:0] a; // no explicit declaration - net is unsigned
input [7:0] b;
input signed [7:0] c;
input signed [7:0] d; // no explicit net declaration - net is signed
output [7:0] e; // no explicit declaration - net is unsigned
output [7:0] f;
output signed [7:0] g;
output signed [7:0] h; // no explicit net declaration - net is signed
wire signed [7:0] b; // port b inherits signed attribute from net decl.
wire [7:0] c; // net c inherits signed attribute from port
reg signed [7:0] f; // port f inherits signed attribute from reg decl.
reg [7:0] g; // reg g inherits signed attribute from port
endmodule

module complex_ports ({c,d}, .e(f));
// Nets {c,d} receive the first port bits.
// Name 'f' is declared inside the module.
// Name 'e' is defined outside the module.
// Can't use named port connections of first port.

module split_ports (a[7:4], a[3:0]);
// First port is upper 4 bits of 'a'.
// Second port is lower 4 bits of 'a'.
// Can't use named port connections because
// of part-select port 'a'.

module same_port (.a(i), .b(i));
// Name 'i' is declared inside the module as an inout port.
// Names 'a' and 'b' are defined for port connections.

module renamed_concat (.a({b,c}), f, .g(h[1]));
// Names 'b', 'c', 'f', 'h' are defined inside the module.
// Names 'a', 'f', 'g' are defined for port connections.
// Can use named port connections.

module same_input (a,a);
input a; // This is legal. The inputs are tied together.

module mixed_direction (.p({a, e}));
input a; // p contains both input and output directions.
output e;

Shalom
> -----Original Message-----
> From: owner-verilog-ams@server.eda.org [mailto:owner-verilog-
> ams@server.eda.org] On Behalf Of Jonathan David
> 
> I wouldn't think so, BUT.. is anything like this ever done (and
allowed)
> in the digital Verilog world?
> I would use that principle .. if the digital guys already do this
then
> its ok.. If they don't we shouldn't either
> 
> ----- Original Message ----
> From: Dave Miller <David.L.Miller@freescale.com>

> Is it perfectly valid to have a vector node where some of the elements
> are connected to ports and others are used as internal nodes? I can't
> see anything that explicitly restricts it from a syntax point of view,
> but was wondering if we should disallow it, or leave it intentionally
> ambiguous so that it is up to individual implementations?
> The situation I am referring to is this below.
> 
> module blackbox(in[0]);
>     electrical [0:1] in;
>     analog begin
>        V(in[0]) <+ 5;
>        V(in[1]) <+ 10;
>     end
> endmodule
> 
> Here I have two constant voltage sources, where in[0] is used in a
port
> connection, and in[1] is just a local source. Should this be allowed?