Re: Verilog-AMS Committee Meeting Minutes - Oct 19 2006

All,

If we allow for the support of multiple analog blocks, section 6 "Analog 
Behavior", in particular section 6.1 "Analog procedural block" will need 
to be updated. Instead of the last two sentences in the last paragraph of 
the section a new paragraph should be included describing the support of 
multiple analog blocks and how these blocks interact. I'm referring to the 
last version of "merged_beh.pdf" on the public documents part of the 
Verilog-AMS pages.

The only other location outside section 7 that mentions the restriction to 
a single analog block is section 8.3 "Behavioral interaction", the last 
line of the 1st paragraph. Here I refer to the 2.2 LRM.

Cheers,
Marq


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors










"Martin O'Leary" <oleary@cadence.com> 
Sent by:
owner-verilog-ams@server.eda.org
20-10-2006 06:48

To
"Verilog-AMS LRM Committee" <verilog-ams@server.eda.org>
cc

Subject
Verilog-AMS Committee Meeting Minutes - Oct 19 2006
Classification







Martin O'Leary - Cadence
Graham Helwig - ASTC
Patrick O'Halloran - Tiburon
David Miller - Freescale Semiconductor
Geoffrey Coram - Analog Devices
Boris Troyanovsky - Tiburon


Reviewed Annex D - Standard Definitions.
Also discussed multiple analog block issue for the syntax annex and for
section 7.

discipline ddiscrete
- add semi colon in domain declaration

all disciplines
- add semi colon after every discipline declaration

Action: Dave to update chapter 8 to use ddiscrete instead of logic

Changes were based on a pre2.2 version of annex D.
Action: Geoffrey to send 2.2 version (DONE)
Martin to re-add changes on top of this.

Move the definition of the first 5 constants back to LRM2.0 defs
Add _SPICE and _NIST definitions of P_K and other constants
- Action: Geoffrey to do this before he sends the 2.2 version

Multiple analog blocks in a module justifications
- multiple initial and always blocks are allowed
- fits naturally into syntax
- allows structural generate to work with analog blocks
- allows more flexible structuring of an AMS module
  (e.g. always/analog/initial blocks for same aspect of module can be
put together)
- the simulator would internally combine the multiple analog blocks
  in a single analog block in the order that they appear in the
  module description. In other words, the analog blocks would
  execute in the order that they are specified in the module.
- attendees of meeting agreed with this approach
- action Graham to update the syntax accordingly and Marq
  to update chapter 7 accordingly assuming no issues raised on
  the reflector in the next week.


Spoke about when the LRM should be targetted for completion.
Traditionally it should be done for DAC - target should be DAC'07. Need
to
work back from that.
- Action: Martin to email Sri about when the next board meeting should
be so we can work back the completion date of LRM2.3 from that.

LRM Sections in the pipeline:
* section 8 - David Miller - weeks to submission = 4 (11/16/06)
* section 10 (no table model) - Martin O'Leary - weeks to submission = 5
(11/30/06)
* section 10 (table model) - Patrick O'Halloran - weeks to sumission =
????
* section 7 - Marq Kole - weeks away from submission = ???

Thanks,
--Martin