section 7 posted

All,

A first draft of section 7 has been posted in the public documents area of 
the Verilog-AMS committee's website:

http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/merged_hier.pdf

In general, this is a merger between the section 7 from the Verilog-AMS 
2.2 LRM and the section 12 from the IEEE 1364-2005 LRM. In addition 
relevant bug reports from the Mantis database have been included in the 
changes. 

Here is a detailed survey of what has been changed with respect to the 
same section in the 2.2 LRM:

general
Throughout the document the syntax tables have been updated according to 
the preliminary syntax by Graham Helwig also posted on the Verilog-AMS 
committee's website. Unfortunately the frame document I had was no more 
recent than April 7.
Verilog-AMS code in examples has been formatted in one style:
- everything between module and endmodule keywords is indented
- everything between begin and end keywords is indented
- continued lines are indented
The more formal language from the IEEE has been applied to this section, 
adding "shall" or "must" whenever appropriate (as far as a non-native 
speaker can tell :-) )

introduction
A sentence from the section 12 introduction has been added, to the end of 
the first paragraph.

7.1 modules
The second paragraph now explains the support for multiple analog blocks 
in a module body. This text has been taken from the conference call 
minutes of October 26.
The syntax in table 7-2 has been extended with a few items: the 
analog_construct is now one of the rules in module_or_generate_item, and 
the aliasparam_declaration, branch declaration, and 
analog_function_declaration are not part of the 
module_or_generate_item_declaration, as per request of Graham Helwig 
(email in archive: http://www.eda-stds.org/verilog-ams/hm/1645.html)

7.1.1 top-level modules
The additional constraint from 1364 section 12.1.1 has been added.

7.1.2 module instantiation
A sentence from section 12.1.2 has been added to the end of the first 
paragraph.
The bulleted list of concepts has been changed to regular paragraphs, in 
accordance with IEEE text.
The explanation of a connection that follows this list has been extended 
with additional items from the IEEE section 12.1.2.

7.2 overriding module parameter values
No changes

7.2.1 defparam statement
No changes (except as noted under general)

7.2.2 module instance parameter assignment by order
No changes (except as noted under general)

7.2.3 module instance parameter assignment by name
No changes (except as noted under general)

7.2.4 parameter dependence
no changes

7.2.5 detecting parameter overrides
no changes

7.2.6 hierarchical system parameters
no changes

7.3 paramsets
no changes

7.3.1 paramset statements
no changes

7.3.2 paramset overloading
no changes

7.3.3 paramset output variables
no changes

7.4 ports
no changes

7.4.1 port association
no changes

7.4.2 port declarations
no changes

7.4.3 real valued ports
no changes

7.4.4 connecting module ports by ordered list
No changes (except as noted under general)

7.4.5 connecting module ports by name
No changes (except as noted under general)

7.4.6 detecting port connections
no changes

7.4.7 port connection rules
no changes

7.4.8 inheriting port natures
no changes

7.5 generate constructs
This section has been copied completely from the 1364-2005 LRM, but 
references have been updated to refer to other sections in this document.
In the syntax of table 7-9 the analog_construct has been added to the rule 
for module_or_generate_item.

7.5.1 loop generate constructs
The text in this section has been copied completely from the 1364-2005 
LRM. The bad/invalid examples from the 1364 LRM have been left out, but 
more analog examples have been used to illustrate the use of the loop 
generate construct. For the first example the ADC from the 2.2 LRM, annex 
C.19.3 (generate) has been adapted. The other two examples are series of 
RC sections used to create an interconnect line model.

7.5.2 conditional generate constructs
The text in this section has been copied completely from the 1364-2005 
LRM. The examples show typical (?) analog uses of the conditional generate 
construct. The last example shows the use of recursion to create an ADC 
with parametrized number of bits.
In the last paragraph a reference is made to paramsets to achieve some of 
the same functionality.

7.5.3 external names for unnamed generate blocks
The text in this section has been copied completely from the 1364-2005 
LRM. 
The example from the digital text has been änalogized"by replacing the 
wire declarations by electrical node declarations.

7.6 hierarchical names
no changes

7.7 scope rules
added references to generate blocks as an element that defines a new 
scope.

7.8 elaboration
This section has been copied completly from the 1364-2005 LRM. Inclusion 
was necessary becauseof the generate constructs that make elaboration in 
certain cases ambigous without the rules in subsection 7.8.1.

Cheers,
Marq

 
Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors