Re: compiler directive with formal arguments

Geoffrey,

An overview of who was doing what was published on the reflector nearly a 
year ago by Sri:

http://www.eda.org/verilog-ams/hm/1254.html

It says that Graham is the responsible one...

Cheers,
Marq


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors










"Geoffrey.Coram" <Geoffrey.Coram@analog.com> 
Sent by:
owner-verilog-ams@server.eda.org
09-11-2006 16:01

To
verilog-ams <verilog-ams@server.eda.org>
cc
"Muranyi, Arpad" <arpad.muranyi@intel.com>
Subject
Re: compiler directive with formal arguments
Classification







Who's in charge of updating the compiler directives section?
Please keep in mind Arpad's comments on the example.

-Geoffrey


"Muranyi, Arpad" wrote:
> 
> Geoffrey,
> 
> I haven't been to Mantis for a while and I forgot how to get
> in, so I wasn't able to read that proposal yet.  (I would
> appreciate it if someone could remind me how to get in in a
> private message).
> 
> Does this proposal make the usage of the double quotes around
> the macro text required, or does it say that if they are there
> (optionally) than they will not be printed?  I am looking at
> the 1364-2005 LRM and it seems that this will be a deviation
> from that LRM.  If anything, wouldn't we want to bring the LRM-s
> closer together than deviate further?  Or is that LRM going to
> be updated according to this change too?
> 
> By the way, the example in 1364-2005 is not very helpful...
> 
> `define var_nand(dly) nand #dly
> `var_nand(2) g121 (q21, n10, n11);
> `var_nand(5) g122 (q22, n10, n11);
> 
> The corresponding example in the Verilog-AMS v2.2 LRM is much better:
> 
> //define an adc with variable delay
> `define var_adc(dly) adc #(dly)
> // Given the above macro the following uses
> `var_adc(2) g121 (q21, n10, n11);
> `var_adc(5) g122 (q22, n10, n11);
> // shall result in:
> adc #(2) g121 (q21, n10, n11);
> adc #(5) g122 (q22, n10, n11);
> 
> I really wish we had a single LRM only...
> 
> Thanks,
> 
> Arpad