Re: Verilog-AMS Committee Meeting Reminder - 10 Nov 2006 (DIFFERENT TIME!)

All,

Apparently something went wrong in maing this appointment: the date stated 
is the 10th, but the weekday mentioned in the table of local times was 
Thursday. I propose we postpone this week's call to next week, Thursday 
16th (I checked my calender now), again at 3 PM Pacific. The agenda 
remains the same, but please come forward if the proposed time is awkward 
in any particular way.

Cheers,
Marq


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors










Marq Kole <marq.kole@nxp.com> 
Sent by:
owner-verilog-ams@server.eda.org
08-11-2006 22:24

To
"verilog-ams" <verilog-ams@server.eda.org>
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Subject
Verilog-AMS Committee Meeting Reminder - 10 Nov 2006 (DIFFERENT TIME!)
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Hi all, 

Date & Time: 10th Nov 2006, 3:00-4:00pm Pacific

Call-In Details:
  USA Toll Free Number: 877-346-8823
  USA Toll Number: +1-203-320-0407 (for intl)
  Participant Passcode: 602538

We momentarily spoke about a new time slot for the weekly telephone 
conference. Although we had few people on the call last week, it was 
proposed to move back to the old time this week, and to try to find a good 
common time by then. So the call time for this week will be: 

03:00 PM Pacific   (Thursday) 
06:00 PM Eastern   (Thursday) 
03:30 AM India     (Friday) 
09:30 AM Adelaide  (Friday) 
12:00 PM Amsterdam (Thursday) 
01:00 AM Athens    (Friday) 

Agenda:
   * Review of section 7 "Hierarchical Structures" , continuing with 
section 7.5.2.
   * Status of upcoming review work (what's next) 
   * Reconsideration of meeting time 

   No update of the section 7 document has been posted - that will be done 
after the first 
    round of review is finished. 
    The current document has been uploaded to the public document section 
of the Verilog-AMS 
    website.
   http://www.eda.org/verilog-ams/htmlpages/public-docs/merged_hier.pdf

Thanks,
Marq


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors