updated section 7

All,

An updated version of section 7 "Hierarchical Structures" will be 
available shortly from the Verilog-AMS standardization website at:

http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/merged_hier.pdf

while the previous version of the document should be available at:

http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/merged_hier_v1.0.pdf

The following changes have been made to the document (merged_hier.pdf) 
with respect to the previously posted document (merged_hier_v1.0.pdf); 
unless noted differently, these are the changes as proposed during the 
November 2 conference call, and noted in the minutes of that call.

section 7.1, p. 125, 2nd paragraph, 1st line: "A module definition may 
have multiple analog blocks."

section 7.1, p. 127, syntax 7-2: aliasparam_declaration has been moved to 
non_port_module_item.

Contrary to the initial discussion results during the conference call, 
I've left the analog_function_declaration in the 
module_or_generate_item_declaration to not increase the differences 
between function_declaration and analog_function_declaration. This needs 
to be discussed again during the next conference calls.

section 7.1.2, p. 128, last paragraph, 2nd sentence: "An expression can be 
used for supplying a value to a module input port, if it is a digital port
."

section 7.1.2, p. 129, example 1, removed the ground declaration from 
module comparator, and added it to module sigmadelta.

section 7.2.1, p. 131, example: added empty parentheses after the name of 
module tgate; changed the instances of mosp and mosn to use all port names 
in the order "drain, gate, source"; changed typography of a couple of 
words to non-keyword type.

section 7.2.1, p. 132, example: added empty parentheses after the name of 
module annotate.

section 7.2.2, p. 132, example: added empty parentheses after the name of 
module m.

section 7.3.1, p. 138, example: added empty parentheses after the name of 
module semicoCMOS.

section 7.5, p. 149, syntax 7-10: added newlines to make 
case_generate_item and case_generate_construct well formed syntax items.

section 7.5.1, p. 151, examples: changed the module headings to use 
regular LRM 2.2 syntax; added lines for shorting the output nodes n1 and 
n2 to the ends of internal node vector n; changed typography of the words 
"electrical" to non-keyword type; changed typography of words "analog" and 
"ddt" to keyword type.

The following changes are ahead of the review, but needed changing anyway.

section 7.5.2, p. 153, examples: changed typography of the words 
"electrical" to non-keyword type.

section 7.5.2. p.154, example: changed typography of word "module" to 
keyword type.

section 7.5.3. p.154, example: added empty parentheses after the name of 
module top.

section 7.6, p. 156, examples: changed the indentation to follow the style 
of the other examples in section 7.

Cheers,
Marq


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors
Tel: +31 40 27 49051, Fax: +31 40 27 44700, Mobile: +31 6 387 48 389
High Tech Campus 48 p.2.039, 5656 AE Eindhoven, The Netherlands
marq.kole@nxp.com, www.nxp.com