Re: Why is type for string parameters mandatory?

Actually i might be wrong in one thing that I mentioned. I think we took 
the string parameter definition from SystemVerilog. Need to check that 
and also verify whether it was compulsory to specify the type for string 
parameters.

Also, as i mentioned earlier its possible that we might have made it 
mandatory to specify the type for the syntax checker since this 
parameter declaration syntax was slightly different to integer and real 
parameters.

However i someone does

parameter myParam = "abc";

whether this would be treated as integer and what the value of the 
integer would be. I need to check this by running on the simulator. 
Probably an error?

cheers,
Sri

Sri Chandra wrote:
> Dave,
> 
>  From what i remember we created a new syntax for string parameters. I 
> don't think string parameters exists in either 1364 or P1800 and the 
> purpose for this was bit different to the registers specified in 1364. 
> As Marq mentions this was specifically used so that model writes can use 
> it in comparison functions or as arguments and control the value of the 
> strings that can be used using the from/to parameter syntax.
> 
> Infact, the from/to syntax was also slightly modified to accommodate 
> string parameters.
> 
> cheers,
> Sri
> 
> 
> Marq Kole wrote:
>>
>> Dave,
>>
>> Do these digital simulators use these string parameters as we do, or 
>> can they assign these string parameters as default values to string 
>> registers?
>>
>> As far as I can tell in AMS you can only compare string parameters 
>> against string constants or other string parameters, or use them as a 
>> string argument in display tasks. No connection is made between the 
>> string parameters in AMS and the string registers in 1364-2005.
>>
>> Does SystemVerilog have (extended) support for string parameters?
>>
>> Cheers,
>> Marq
>>
>>
>> Marq Kole
>> Competence Leader Robust Design
>>
>> Research
>> NXP Semiconductors
>>
>>
>>
>>
>>
>>
>>
>>
>> *Dave Miller <David.L.Miller@freescale.com>*
>>
>> Sent by:
>> owner-verilog-ams@server.eda.org
>>
>> 14-11-2006 18:22
>>
>>     
>> To
>>     Verilog-AMS LRM Committee <verilog-ams@server.eda.org>
>> cc
>>     
>> Subject
>>     Why is type for string parameters mandatory?
>> Classification
>>     
>>
>>
>>     
>>
>>
>>
>>
>>
>> Hi all,
>> I am just wondering why do we explicitly say that the type specification
>> for a string parameter is mandatory?
>> Why can't we allow the type to be derived based upon the default
>> expression.
>> Do you think we could remove this restriction in 3.2.1 and just mention
>> that if no type is specified and the parameter is assigned a default
>> value of a string, then the type of the parameter will be string and it
>> will be an error if the parameter is overridden with any numerical value.
>> This is causing me some problems at the moment as some digital
>> simulators that I am using allow string parameters to be defined without
>> the type. In fact if I understand digital correctly (2005) you can't
>> actually have a string parameter (only string registers) but that is a
>> separate issue.
>>
>> Dave
>>
>> -- 
>> =====================================
>> -- David Miller
>> -- Design Technology (Austin)
>> -- Freescale Semiconductor
>> -- Ph : 512 996-7377 Fax: x7755
>> =====================================
>>
>>
> 

-- 
Srikanth Chandrasekaran
DTO Tools Development
Freescale Semiconductor Inc.
Ph: +91-120-439 7021 F: x5199