RE: Verilog-AMS Committee Meeting Minutes - Nov 16 2006

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Sun Nov 19 2006 - 11:26:09 PST
You probably already know this, but 1364-2005 says,

 

"12.1.1 Top-level modules

Top-level modules are modules that are included in the source text, but
do not appear in any module

instantiation statement, as described in 12.1.2. This applies even if
the module instantiation appears in a

generate block that is not itself instantiated (see 12.4). A model shall
contain at least one top-level module."

 

Shalom

 

* Marq to ask for the meaning of top-level modules in the digital
community. 
Received on Sun Nov 19 11:27:31 2006

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