RE: Verilog-AMS Committee Meeting Minutes - Nov 16 2006

From: Marq Kole <marq.kole_at_.....>
Date: Mon Nov 20 2006 - 01:00:12 PST

Shalom,

Essentially the same text is part of the Verilog-AMS LRM, but my actual question is: what is the purpose of top-level modules? Why is it not allowed to use a (self-)recursive module as top-level module, if the initial recursion level is defined through the default value of the controlling parameter? It seems to me as overly restrictive...

Cheers,
Marq


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors







"Bresticker, Shalom" <shalom.bresticker@intel.com>

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19-11-2006 20:26

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<verilog-ams@server.eda.org>
Subject
RE: Verilog-AMS Committee Meeting Minutes - Nov 16 2006
Classification





You probably already know this, but 1364-2005 says,
 
“12.1.1 Top-level modules
Top-level modules are modules that are included in the source text, but do not appear in any module
instantiation statement, as described in 12.1.2. This applies even if the module instantiation appears in a
generate block that is not itself instantiated (see 12.4). A model shall contain at least one top-level module.”
 
Shalom
 
* Marq to ask for the meaning of top-level modules in the digital community.

Received on Mon Nov 20 01:06:33 2006

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