Re: Verilog-AMS Committee Meeting Minutes - Nov 16 2006

Marq -
Now I remember the issue with the paramsets: the mismatch paramset
on page 138 of LRM 2.2 (section 7.3.1) has
.tox = semicoCMOS.tox + semicoCMOS.dtox_g + semicoCMOS.dtox_mm;

where "semicoCMOS" is the module identifier, but it should be
the instance name, eg

semicoCMOS process();


On the other hand, if semicoCMOS is not instantiated, then it is
a top-level module.  I vaguely recall something about the 
instance name for a top-level module being the module identifier,
so maybe the example works.


On a related note, neither in 7.1.1 nor in 12.1.1 that Shalom cited
from 1364-2005 do I see any requirement that top-level modules have
no ports (or any indication of what one does with such ports, if
there are some).  Can top-level modules have ports?

Also: what about libraries?  1364-2005 (and the "merged" AMS syntax)
has a new syntax category of "library_text" -- are modules defined
in a library but not instantiated treated differently than those in
the regular source text?  Eg, in Spice, one has a .lib that contains
all the model cards, and the simulator picks out the ones it needs;
model cards that are not used do not become top-level modules.

-Geoffrey