Re: Verilog-AMS Committee Meeting Reminder - 30 Nov 2006

From: Dave Miller <David.L.Miller_at_.....>
Date: Wed Nov 29 2006 - 06:14:40 PST
And just so Graham doesn't have a heart attack, that is 3:30 PM Adelaide 
time :)

Dave

Sri Chandra wrote:
> Sorry, the date in the body of the email should read 30th November. 
> (thanks Jim)
>
> cheers,
> Sri
>
> Sri Chandra wrote:
>> Hi all,
>>
>> Date & Time: 17th Nov 2006, 9-10pm Pacific
>>
>> Call-In Details:
>>  USA Toll Free Number: 877-346-8823
>>  USA Toll Number: +1-203-320-0407 (for intl)
>>  Participant Passcode: 602538
>>
>> The new call times are:
>>
>> 09:00 PM Pacific   (Thursday)
>> 11:00 PM Central   (Thursday)
>> Midnight Eastern
>> 07:00 AM Eindhoven (Friday)
>> 10:30 AM India     (Friday)
>> 03:30 AM Adelaide  (Friday)
>>
>> Agenda:
>>   * Review the updated Section 7 "Hierarchical Structures"
>>     - new subsection 7.5.2.1
>>     - new sections 7.8.1, 7.8.2, 7.8.3, 7.8.4
>>     - Document available at: 
>> http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/merged_hier.pdf 
>>
>>
>>   * Briefly go over some of the discussions I have had with Karen 
>> Pieper (SV Committee) with regards to AMS and P1800 standards
>>
>> cheers,
>> Sri
>


-- 
=====================================
-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
=====================================
Received on Wed Nov 29 06:14:47 2006

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