From: Marq Kole <marq.kole_at_.....>
Date: Thu Dec 07 2006 - 22:22:09 PST
Ken,
The simple model of an opamp in your
proposal does not seem to be working as an opamp. If I wire it up with
two resistors as a feedback amplifier and feed it a pulse waveform, it
does not give me back an amplified version of the input signal, but rather
an integration of the pulse waveform. To prevent confusion I would propose
to simply call it an integrator.
Cheers,
Marq
Marq Kole
Competence Leader Robust Design
Research
NXP Semiconductors
Ken Kundert <ken@designers-guide.com>
Sent by:
owner-verilog-ams@server.eda.org
06-12-2006 23:32
To
Sri Chandra <sri.chandra@freescale.com>
cc
VerilogAMS Reflector <verilog-ams@server.eda.org>
Subject
Re: idt reset issue
Classification
Sri,
Yes, I think I can make it. I have created a proposal and
Geoffrey
posted it on the website:
http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/idt-proposal.pdf
-Ken
Sri Chandra wrote:
> Hi Ken,
>
> Would you be available 9pm Pacific this thursday (Dec 7th) to discuss
> the idt proposal along with the proposed changes. If you can send
the
> proposal across before the meeting that will be good.
>
> cheers,
> Sri
>
> Sri Chandra wrote:
>> Ken,
>>
>> By the way just thought will let you know that the timings of
the
>> meeting has changed (from this week onwards). Now-a-days the meetings
>> are on thursday evenings at 9pm pacific.
>>
>> Please go ahead and send out a proposed change to the committee
based
>> on the feedback that you received on the reflector. We can review
that
>> as part of the meeting. Since idt is a very key item, and a fairly
>> major feature in Verilog-A quiet widely used, I would be very
>> uncomfortable changing the LRM without actually having a live
>> discussion in the call. So hopefully you would be able to attend
one
>> of the upcoming meetings at this new time and we can discuss the
new
>> document that you plan to post.
>>
>> Hope that is agreeable.
>>
>> Regards,
>> Sri
>>
>> cheers
>>
>> Ken Kundert wrote:
>>> Sri,
>>> I have an on-going conflict that prevents me
from calling into the
>>> meetings. I have published a description of the problem and
the desired
>>> behavior. There has been some discussion on the reflector
and nobody has
>>> presented any objections. Perhaps I should just send out a
proposed
>>> change to the LRM and see what everyone thinks?
>>>
>>> -Ken
>>>
>>> Sri Chandra wrote:
>>>> Ken,
>>>>
>>>> I haven't been able to attend the recent calls but I hope
to be back
>>>> online from this week onwards. I dont think this issue
has been
>>>> discused
>>>> in the recent meetings. The committee has been reviewing
independent
>>>> chapters and we are currently in the process of reviewing
chapter 7
>>>> being edited by Marq Kole.
>>>>
>>>> The last I remember in the reflector was you were planning
to present
>>>> this item to go over it to the committee but you were
unable to attend
>>>> the meeting. If you are available and if you can present
the
>>>> proposal at
>>>> one of the the committee meetings that will be great and
we can
>>>> schedule
>>>> it in one of the upcoming calls.
>>>>
>>>> Regards,
>>>> Sri
>>>>
>>>> Ken Kundert wrote:
>>>>> Sri,
>>>>> Was there any decision made on
the idt issue? Would you like
>>>>> me to
>>>>> a cut at refining the description of idt in the LRM
to avoid the
>>>>> ambiguity in its behavior?
>>>>>
>>>>> -Ken
>>>>>
>>>>> Ken Kundert wrote:
>>>>>> All,
>>>>>> I apologize for missing the call
this morning. It turns out that
>>>>>> Thursday mornings are just too busy for me to
attend.
>>>>>>
>>>>>> I have updated the document to include an model
that patterns the
>>>>>> desired behavior. You can find the updated version
at
>>>>>> http://designers-guide.org/private/vams-extensions/idt-issue.pdf
>>>>>>
>>>>>> Also, I would like to offer the use the my online
forum for use by
>>>>>> the
>>>>>> Verilog-AMS committee. We used it when defining
the compact model
>>>>>> extensions and I found it to be a very convenient
way to carrying
>>>>>> on the
>>>>>> conversations about particular issues. It naturally
separates the
>>>>>> discussion threads and makes them easy to follow.
If you wanted to do
>>>>>> this, I would give you a private board, so only
invitees would be
>>>>>> allowed to see the board or contribute.
>>>>>>
>>>>>> -Ken
>>>>>>
>>>>>>
>>>>>> Geoffrey.Coram wrote:
>>>>>>> Resending for Ken Kundert; original message
bounced (too long).
>>>>>>> Attachment has been saved as
>>>>>>> http://www.verilog.org/verilog-ams/htmlpages/public-docs/idt-issue.pdf
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> ----------------- Original Message -------------
>>>>>>> All,
>>>>>>> I'd like to join the meeting
tomorrow and discuss the reset
>>>>>>> feature
>>>>>>> of the idt function. I have not had much luck
using this feature
>>>>>>> through
>>>>>>> the years, and recently had a situation where
I really needed it.
>>>>>>> Unfortunately, I found the Cadence implementation
unsuitable once
>>>>>>> again,
>>>>>>> and when I dug in to it I found the LRM silent
on critical
>>>>>>> aspects of
>>>>>>> this feature. I have attached a very short
document that illustrates
>>>>>>> the
>>>>>>> issue and proposes what I believe to be the
desirable behavior.
>>>>>>> If you
>>>>>>> all agree I will work on coming up with the
needed modifications to
>>>>>>> the LRM.
>>>>>>>
>>>>>>> -Ken
>>
>
[attachment "ken.vcf" deleted by Marq Kole/EHV/RESEARCH/PHILIPS]
Received on Thu Dec 7 22:24:31 2006
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