From: Marq Kole <marq.kole_at_.....>
Date: Fri Dec 08 2006 - 00:26:09 PST
Jonathan,
Yeah, but for contribution you probably
want the contributing OOMR signal to be part of the discipline resolution
for the whole design, while for RHS that is not really needed. To put it
in another way: for contribution you actually want the behavior of the
design to change, while for reading/probing (again considering the test
bench use) you do not want a different behavior because of the reading/probing.
Cheers,
Marq
Marq Kole
Competence Leader Robust Design
Research
NXP Semiconductors
Jonathan David <jb_david@yahoo.com>
08-12-2006 08:08
To
Marq Kole <marq.kole@nxp.com>
verilog-ams <verilog-ams@eda-stds.org>
cc
Subject
Re: Hierarchical reference questions
Classification
One implication of this is that its ONLY
for RHS expressions..
you'd have to Coerce to do a heirarchical contribution.
But it does seem more flexible
----- Original Message ----
From: Marq Kole <marq.kole@nxp.com>
To: verilog-ams <verilog-ams@eda-stds.org>
Sent: Thursday, December 7, 2006 10:37:55 PM
Subject: RE: Hierarchical reference questions
Martin,
Instead of the proposed "useas" keyword would you suggest that
we can also fit the casting operation to our needs? So for Graham's example:
myDesign system(.....);
//electrical system.inst.inst.net; // not needed
//logic system.inst.net; //
not needed
analog $display("Value is %g.", V(electrical'(system.inst.inst.net)));
initial $display("Value is %b.", logic'(system.inst.net));
As a way to handle OOMR I like this better than the "useas" keyword.
Here is something from section 4.14 "Casting" of SystemVerilog
that
talks about how casting is done in that language.
> A data type can be changed by using a cast ( ' ) operation. In a
static cast, the expression to be cast
> shall be enclosed in parentheses that are prefixed with the casting
type and an apostrophe. If the
> expression is assignment
> compatible with the casting type, then the cast shall return the value
that a variable of the casting
> type would hold after being assigned the expression. If the expression
is not assignment compatible
> with the casting type, then if the casting type is an enumerated type,
the behavior shall be as
> described as in 4.15, and if the casting type is a bit-stream type,
the behavior shall be as
> described in 4.16.
Here is an example of how a real expression is cast to an int.
> int'(2.0 * 3.0)
Thanks,
--Martin
-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Jonathan David
Sent: Thursday, December 07, 2006 9:55 PM
To: Graham Helwig; Verilog-AMS Reflector
Subject: Re: Hierarchical reference questions
----- Original Message ----
From: Graham Helwig <graham.helwig@astc-design.com>
To: Verilog-AMS Reflector <verilog-ams@eda.org>
Sent: Wednesday, December 6, 2006 11:46:38 PM
Subject: Hierarchical reference questions
Hello,
When simulating large mixed-signal design (containing transistors and
gates) I have had the need to hierarchically reference an implicit net
with the design. Also the resolved domain of the net is not known and
even if it is known it may change from one simulation to the next.
I may of missed in the LRM, but is hierarchical referencing of an
implicit nets allowed in the language?
If it is, then does the net need to be coerced to the same domain as the
probe or does discipline resolution and ACMI resolves handle the
resolution of the implicit net including any hierarchical references to
that net?
For example:
myDesign system(.....);
electrical system.inst.inst.net; // is this required?
logic system.inst.net; //
is this required?
analog $display("Value is %g.", V(system.inst.inst.net));
initial $display("Value is %b.", system.inst.net);
Regards
Graham
--
==========================================================
Graham Helwig
AMS Verification
Australian Semiconductor Technology Company (ASTC) Pty Ltd
Location: 76 Waymouth St, Adelaide, SA, 5000, Australia
Phone +61-8-82312782
Moblie: +61-4-03395909
Email: graham.helwig@astc-design.com
Web: www.astc-design.com
==========================================================
Received on Fri Dec 8 00:27:52 2006
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