Re: Elaboration algorithm proposal

edaorg@v-ms.com wrote:
>
> This sounds bad to me. As a user I would expect to get the
> same behavior if I put the analog blocks in the same module
> or in separate modules if their connectivity is the same -
> I don't see that being the case if the blocks get concatenated.
> Reodering always blocks in Verilog doesn't change the behavior,
> the same should be true for analog blocks.
> 
> I think there should be an explicit statement to the effect
> that: the reordering of analog blocks within a module or
> declaring them in seperate modules should not change the
> results of simulation for pure analog (to exclude A/D issues
> at ports).

Kevin brings up an interesting point: what about value
retention?  If I do:
  analog begin: block 1
    V(out) <+ 5;
  end
  
  analog begin: block 2
    I(out) <+ 5;
  end

Then reordering the blocks before concatenation will
alter the results.

Also, if you have 
  analog begin: block 1
    V(out) <+ 5;
  end
  
  analog begin: block 2
    V(out) <+ 500;
  end
then you will get a singular matrix error if these 
are in separate modules connecting to the same node.
If they are concatenated, the values will add and
you'll get a 505-volt independent source driving
the node.

-Geoffrey