Re: Elaboration algorithm proposal

edaorg@v-ms.com wrote:
> Marq Kole wrote
> Concatenation of the analog blocks occurs after all generate 
> constructs have been evaluated, i.e. after the loop generate 
> constructs have been unrolled, and after the conditional generate 
> constructs have been selected. If an analog block appears in a loop 
> generate statement then the order in which the loop is unrolled during 
> elaboration determines the order in which the analog blocks are 
> concatenated to the eventual single analog block after elaboration.
> This sounds bad to me. As a user I would expect to get the same 
> behavior if I put the /analog/ blocks in the same module or in 
> separate modules if their connectivity is the same - I don't see that 
> being the case if the blocks get concatenated. Reodering /always/ 
> blocks in Verilog doesn't change the behavior, the same should be true 
> for /analog/ blocks.
>
> I think there should be an explicit statement to the effect that: the 
> reordering of /analog/ blocks within a module or declaring them in 
> seperate modules should not change the results of simulation for pure 
> analog (to exclude A/D issues at ports).
>
> Kev.
>>
But the order of the analog blocks and execution of them does change the 
simulation results. Ignoring generate blocks, consider just a situation 
of two analog blocks in the one module.

module bb();
    electrical a;
    real x;
    analog begin
       x = x + 5;
       V(a) <+ x;
    end
    analog begin
       x = 1;
    end
endmodule

V(a) gets the value of 5, 6, 6, 6, .......

Swap them around and V(a) gets 6, 6, ....

Okay not the best example but you get what I mean.

So the analog blocks should be concatenated in the order that they are 
written, and the user should be aware that assignment statements in 
particular are executed in a procedural manner.

Dave

   

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-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
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