Re: paramset resolution

Kevin Cameron wrote:
>
> [Is there a rationale somewhere for allowing unconnected ports?]
> 
> This sounds to me like something that needs explicit syntax to say that
> it is OK to leave ports unconnected. Just using the "fewest unconnected
> ports" seems pretty arbitrary, and presumably the more complicated
> (accurate?) a model the more likely it would be to have unconnected
> ports so the bias would be to using less accurate models.

I think that's right: if you didn't specify all the connections,
then you're content with a less-accurate -- and presumably faster! --
model.

Eg, if you don't specify the substrate connection of a bipolar,
you're content with a 3-terminal model.

Digital Verilog doesn't require you to connect all your ports,
and there's no special syntax required.  Eg, your clock module
could have clk and clkbar, but you only need clk.

-Geoffrey