Geoffrey.Coram wrote: > Kevin Cameron wrote: > >> [Is there a rationale somewhere for allowing unconnected ports?] >> >> This sounds to me like something that needs explicit syntax to say that >> it is OK to leave ports unconnected. Just using the "fewest unconnected >> ports" seems pretty arbitrary, and presumably the more complicated >> (accurate?) a model the more likely it would be to have unconnected >> ports so the bias would be to using less accurate models. >> > > I think that's right: if you didn't specify all the connections, > then you're content with a less-accurate -- and presumably faster! -- > model. > I prefer to have things "fail safe", i.e. default to the behavior that's least likely to be wrong (use the accurate model). Bad silicon is expensive. As a user you don't want tools making the wrong assumptions for you. > Eg, if you don't specify the substrate connection of a bipolar, > you're content with a 3-terminal model. > If you are only looking at a few lines of code then that's fine. The paramset mechanism is going to be used with potentially hundreds of models specified in thousands of lines of machine generated code. It's important to minimize the opportunity for error. > Digital Verilog doesn't require you to connect all your ports, > and there's no special syntax required. Eg, your clock module > could have clk and clkbar, but you only need clk. > Digital doesn't do module overloading, and has a bunch of legacy issues which make lint tools a viable market. As I said above, you want to reduce the opportunity for error by using strict syntax and well defined semantics whenever possible. Kev. > -Geoffrey > >Received on Fri Dec 15 11:09:18 2006
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