Re: multiple analog blocks

Kevin Cameron wrote:
> 
> Would you like to comment on the fact that there is only one VHDL, while
> there are ~ 3 flavors of Verilog?

Would you like to comment on why essentially all the compact
model development teams are using Verilog-A instead of VHDL-AMS?
(those that aren't still coding in C to the rather dated
Spice3 interface)

Both the two standard BJT models (Mextram, HiCuM); the
standard next-gen MOS model (PSP) -- as well as several
of the candidates that were not selected; two of the
LDMOS models (MOS20, also available in C, and HV-EKV,
I'm guessing HV-HiSIM is in C); ... all in Verilog-A.

I've never seen a VHDL-AMS model presented to the Compact
Model Council.  So, apparently, having one VHDL doesn't
make it a better solution.  Having all the digital baggage
apparently does make it harder to include in a simulator,
because none of the pure analog simulators have VHDL
support.


> I was there, and the design objectives were documented:
> 
> http://eda.org/verilog-ams/htmlpages/dod.html
> 
> - not much mention of Verilog-A a subset.

Under section 2, General, I see:
  A subset of Verilog-AMS must be defined that is suitable for
  description and simulation of continuous time systems at several levels.

What subset is that, if not Verilog-A?

Also, Verilog-A is mentioned explicitly in 2.2.


-Geoffrey