Re: multiple analog blocks

Geoffrey.Coram wrote:
> Kevin Cameron wrote:
>   
>> The meaning of "The domain of a variable is that of the context
>> from which its value is assigned." in 8.2.2 is not clear, and
>> variables don't actually need to be assigned a domain, only
>> drivers and receivers need to be considered as belonging a
>> domain, but there is no real reason you can't assign to
>> "analog" objects in a digital process or "digital" objects
>> from an analog.
>>     
>
> I haven't really though through all the ramifications, and
> I don't really know what "drivers" and "receivers" are for
> a compact model ... but the LRM also says "the derivative
> with respect to time of a digital value is always zero (0)."
>
> So, now if I have 
>   I(a,c) <+ ddt(qdep);
> where qdep is usually computed in the analog section, but
> at some points in the digital simulation one sets qdep=0,
> then what happens to the current?
>   
[I should have said drivers, receivers and contributions (an analog 
driver).]

That's the kind of case you can easily disallow if you want, but then 
again the definition of the derivative is probably wrong: it should 
probably be something like: "positive infinity on a positive edge, 
negative infinity on a negative edge, NaN for transition to X and 0 
otherwise". Unless you wake up the analog process on changes in qdep 
there should be no problem evaluating the statement, if it doesn't do 
what you want or the matrix solver fails that's a different problem. If 
qdep is a variable it's value is discrete wherever it is used, if qdep 
is a signal then you can't update it directly from a digital context (a 
D2A will be inserted).

I write C/C++ for a living, not ADA. The philosophy of outlawing 
constructs that can be abused belongs to ADA rather than C/C++.

Most programmers who need their code to run fast use C/C++, and I never 
heard a user say their simulator was fast enough.

[IMO] Verilog and VHDL mirror C/C++ and ADA in approach.

>   
>>> A major benefit of Verilog-A (over VHDL-AMS) is, in fact, that it *is*
>>> a proper language, with a well-defined subset defined in the LRM.
>>>
>>>       
>> Not really, the fact that OVI agreed to let Verilog-A exist
>> as an intermediate step has led to people treating it as a
>> standalone language, but it was never meant to exist for long.
>> The original goal was to have a single AMS language. Ken
>> campaigned for the subset approach and after the Verilog-A LRM
>> was released he and the other Cadence representatives on this
>> committee went to great lengths to stall the process of
>> releasing a Verilog-AMS LRM. That's why SystemVerilog is now
>> a separate standard off at the IEEE without any analog capability.
>>     
>
> I would say that the fact that Verilog-A is a well-defined
> standard is the reason why it has been formally adopted as 
> the language of choice for most of the compact model
> development teams and why the GEIA Compact Model Council
> accepts models in Verilog-A for standardization.
>   
Would you like to comment on the fact that there is only one VHDL, while 
there are ~ 3 flavors of Verilog?
> That SV has no analog capability is a separate issue, which
> continues to this day, evidenced by the fact that there is 
> still little commitment from the SV committees to merging in
> AMS.
>   
Agreed, but that is because people on this committee failed to integrate 
Verilog-AMS into Verilog before it headed to the IEEE, and given that 
Verilog-AMS also predates SuperLog and Vera as a standard by a fair 
margin I think it's somewhat embarrassing.
> Of course, the origins of Verilog-A were well before my time
> on this committee, so I don't know what OVI's intention was --
> nor Ken's, and I don't think it's appropriate to speculate.
>   
I was there, and the design objectives were documented:

http://eda.org/verilog-ams/htmlpages/dod.html

- not much mention of Verilog-A a subset.

Kev.
> -Geoffrey
>
>