Re: multiple analog blocks & holiday cheer

Jonathan Sanders wrote:
> Kevin,
>
> Glad to see something never change.   You are very consistent on 
> blaming Ken and Cadence.  Whether it was something Cadence proposed 
> that got approved or one of your solutions that got defeated it is 
> nice to know that Ken and Cadence are to blame.  Since I joined in 
> those days Cadence only had one vote so it must have been a pretty 
> awesome vote.
Cadence's influence extends quite far, and most of the damage to the 
language semantics was done before you joined the committee (although 
you were very keen to make sure nothing got changed - "the customers 
aren't complaining").

Actually, since big companies do this kind of thing anyway I think the 
blame falls partly with certain parties at OVI/Accellera who let them 
get away with it, but the stalling tactics outside of the issues 
discussed in the committees to do with patents were all Cadence.

Then again, since OVI was basically set up by Cadence to get the rubber 
stamp of approval on Verilog in the face of competition from VHDL, so 
why should I expect anything different.
> I do remember numerous other companies vote for everything in the LRM 
> no matter where the solution came from, and yes Cadence lost a few 
> votes along the way but maybe their votes did not count?   Of course 
> maybe before I joined Cadence had more than half of the votes and sent 
> the standard down a path of no return.
It's never been a "path of no return", there's nothing in Verilog-AMS, 
SystemVerilog or VHDL that can't be fixed (which is why I'm still 
bringing up the issues). However it does seem to be a path of 
no-convergeance.
>
> Anyway with historians like you there is no telling what the future 
> might say about the past.   SystemVerilog was not even a thought in 
> those days but glad to see its future with AMS was doomed by Cadence 
> even before it was created, I'm sure that was the plan but I'll have 
> to go back to my notes on that one to confirm :)
Maybe you would care to share your opinions on why there isn't a single 
[System]Verilog-AMS language at this point. The folks at the IEEE 
working on VHDL managed to get their AMS stuff integrated in a 
relatively short time frame and in no way is VHDL a simpler language 
than Verilog.

On the flip-side I find it hard to blame Cadence for the shortcomings of 
SystemVerilog - that was mostly the fault of folks at Synopsys :-)

Kev.
>
> -jons
>
>
> At 10:35 AM 12/21/2006, you wrote:
>> Not really, the fact that OVI agreed to let Verilog-A exist as an 
>> intermediate step has led to people treating it as a standalone 
>> language, but it was never meant to exist for long. The original goal 
>> was to have a single AMS language. Ken campaigned for the subset 
>> approach and after the Verilog-A LRM was released he and the other 
>> Cadence representatives on this committee went to great lengths to 
>> stall the process of releasing a Verilog-AMS LRM. That's why 
>> SystemVerilog is now a separate standard off at the IEEE without any 
>> analog capability.
>
>
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