Re: multiple analog blocks

From: Kevin Cameron <kevin_at_.....>
Date: Thu Dec 21 2006 - 15:19:17 PST
Dave Miller wrote:
>
>> Geoffrey,
>> relying on compiler optimization to extract the initialization
>> statements
>> does lead to other issues (beyond work for the compiler implementator!).
>>
>> In some situations it is not possible for the optimizer to figure out
>> what the user wants.
>> Putting once off calculations in some kind of initial block makes the
>> intent much
>> clearer to compiler (and probably to others who read the model as well).
>>
>> Two examples to consider are;
>>
>> Example 1:
>>
>> module foo;
>> parameter h = 6;
>>
>> real y;
>>
>> analog begin
>>   y = h^2;
>>   if (y > 12.3) $strobe ("warning y is out-of-range");
>> ...
>> endmodule
>>
>> The LRM requires that the warning would be printed every timestep but
>> this may not be what the user
>> intends, because y is just dependent on a parameter and maybe the user
>> just wants the calculation of y and the warning to be printed just once.
>>   
>
> I hate to add another question to all this but I can't help myself and 
> I saw it mentioned in a previous email from someone. Why is it that we 
> are not allowing variable initialisation when declaring analog variable?
Probably just legacy compatibility reasons.
>
> With this we could then simply use constant functions and then we have 
> a ready to go method to perform complex pre-simulation initialisation.
What's telling the compiler it's a constant function, and does it have 
to be?
> Example 1 could be:
> module foo
> parameter h = 6;
>
> analog function real check_range;
>    input val, threshold
>    real val, threshold;
>    begin
>       check_range = val^2;
>       if(val > threshold) $strobe("warning val is out-of-range");
>    end
> endfunction
>
> real y = check_range(h, 12.3);
> analog begin
>    ...
> endmodule
>
> And example 2 would simply be:
> real out = $random();
>
> Dave
>
Can't remember what SV is doing in this area, but you can make life 
easier for the compiler if you add "const":

 const real y = check_range(h, 12.3);
 analog begin
   ...
 endmodule

- otherwise it might be modified by OOMR.

Being able to add the "const" is a definite plus over doing things in an 
initial block.

Would that be considered a "context free" assignment (by 8.2.2)?

Kev.
 
Received on Thu Dec 21 15:19:19 2006

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