Re: multiple analog blocks

Kev,

A const variable declaration (isn't that an oxymoron) is essentially the 
same as a localparam declaration. Both require an initialization and 
localparams are already part of the language (even just the Verilog-A 
subset). The only difference is that the places where localparams can be 
declared are more restricted than those for variables.

Analog functions have some severe restrictions which as far as I can tell 
guarantee that if you call them with the same arguments, they will produce 
the same results. So essentially you should be able to call a UDAF 
(User-Defined Analog Function) during a localparam declaration. There's 
probably some additional constrainsts for handling $random() calls and the 
likes.

Cheers,
Marq


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors









Kevin Cameron <kevin@sonicsinc.com> 
Sent by:
owner-verilog-ams@server.eda.org
22-12-2006 00:19

To
verilog-ams <verilog-ams@server.eda-stds.org>
cc
Dave Miller <David.L.Miller@freescale.com>
Subject
Re: multiple analog blocks
Classification







Dave Miller wrote:
>
>> Geoffrey,
>> relying on compiler optimization to extract the initialization
>> statements
>> does lead to other issues (beyond work for the compiler 
implementator!).
>>
>> In some situations it is not possible for the optimizer to figure out
>> what the user wants.
>> Putting once off calculations in some kind of initial block makes the
>> intent much
>> clearer to compiler (and probably to others who read the model as 
well).
>>
>> Two examples to consider are;
>>
>> Example 1:
>>
>> module foo;
>> parameter h = 6;
>>
>> real y;
>>
>> analog begin
>>   y = h^2;
>>   if (y > 12.3) $strobe ("warning y is out-of-range");
>> ...
>> endmodule
>>
>> The LRM requires that the warning would be printed every timestep but
>> this may not be what the user
>> intends, because y is just dependent on a parameter and maybe the user
>> just wants the calculation of y and the warning to be printed just 
once.
>> 
>
> I hate to add another question to all this but I can't help myself and 
> I saw it mentioned in a previous email from someone. Why is it that we 
> are not allowing variable initialisation when declaring analog variable?
Probably just legacy compatibility reasons.
>
> With this we could then simply use constant functions and then we have 
> a ready to go method to perform complex pre-simulation initialisation.
What's telling the compiler it's a constant function, and does it have 
to be?
> Example 1 could be:
> module foo
> parameter h = 6;
>
> analog function real check_range;
>    input val, threshold
>    real val, threshold;
>    begin
>       check_range = val^2;
>       if(val > threshold) $strobe("warning val is out-of-range");
>    end
> endfunction
>
> real y = check_range(h, 12.3);
> analog begin
>    ...
> endmodule
>
> And example 2 would simply be:
> real out = $random();
>
> Dave
>
Can't remember what SV is doing in this area, but you can make life 
easier for the compiler if you add "const":

 const real y = check_range(h, 12.3);
 analog begin
   ...
 endmodule

- otherwise it might be modified by OOMR.

Being able to add the "const" is a definite plus over doing things in an 
initial block.

Would that be considered a "context free" assignment (by 8.2.2)?

Kev.