Re: multiple analog blocks

Marq Kole wrote:
>
> Dave,
>
> This is very much C/C++ like and in that sense would fit the language 
> quite well. However, I do have some remarks:
>
> First, if you are going to assign to a variable only once, you can 
> also use a localparam, which does support initialization. This 
> initialization is also guaranteed to occur before the first time step.
>
Hi Marq,

Yes I would definitely have used a parameter in real life for that 
particular example.

> Second, one argument Geoffrey brought in is that some initialization 
> cannot be handled in a single line of code, although I can image that 
> by using an analog function this can be partially relieved. Partially, 
> because some initializations require two values to be calculated 
> together. Although analog functions allow for multiple outputs, 
> localparam initialization does not.
>
> Then another concern: this would be diverging from the 1364-2005 
> standard in a part of the syntax that is shared by digital and analog 
> modules; I would rather see that variable initialization is added to 
> the 1364 or 1800 standards first or at the same time. Then again, it 
> does not solve the problem of more complex initializations that cannot 
> be handled in a single line of code.

I don't quite follow. Variable initialization when declaring the 
variable is already part 1364-2005?

Cheers...
Dave

>
> Cheers,
> Marq
>
>
> Marq Kole
> Competence Leader Robust Design
>
> Research
> NXP Semiconductors
>
>
>
>
>
>
>
>
> *Dave Miller <David.L.Miller@freescale.com>*
>
> Sent by:
> owner-verilog-ams@server.eda.org
>
> 21-12-2006 18:35
>
> 	
> To
> 	"Martin O'Leary" <oleary@cadence.com>
> cc
> 	verilog-ams <verilog-ams@server.eda-stds.org>
> Subject
> 	Re: multiple analog blocks
> Classification
> 	
>
>
>
> 	
>
>
>
>
>
>
> > Geoffrey,
> > relying on compiler optimization to extract the initialization
> > statements
> > does lead to other issues (beyond work for the compiler implementator!).
> >
> > In some situations it is not possible for the optimizer to figure out
> > what the user wants.
> > Putting once off calculations in some kind of initial block makes the
> > intent much
> > clearer to compiler (and probably to others who read the model as well).
> >
> > Two examples to consider are;
> >
> > Example 1:
> >
> > module foo;
> > parameter h = 6;
> >
> > real y;
> >
> > analog begin
> >   y = h^2;
> >   if (y > 12.3) $strobe ("warning y is out-of-range");
> > ...
> > endmodule
> >
> > The LRM requires that the warning would be printed every timestep but
> > this may not be what the user
> > intends, because y is just dependent on a parameter and maybe the user
> > just wants the calculation of y and the warning to be printed just once.
> >  
>
> I hate to add another question to all this but I can't help myself and I
> saw it mentioned in a previous email from someone. Why is it that we are
> not allowing variable initialisation when declaring analog variable?
>
> With this we could then simply use constant functions and then we have a
> ready to go method to perform complex pre-simulation initialisation.
> Example 1 could be:
> module foo
> parameter h = 6;
>
> analog function real check_range;
>    input val, threshold
>    real val, threshold;
>    begin
>       check_range = val^2;
>       if(val > threshold) $strobe("warning val is out-of-range");
>    end
> endfunction
>
> real y = check_range(h, 12.3);
> analog begin
>    ...
> endmodule
>
> And example 2 would simply be:
> real out = $random();
>
> Dave
>
> -- 
> =====================================
> -- David Miller
> -- Design Technology (Austin)
> -- Freescale Semiconductor
> -- Ph : 512 996-7377 Fax: x7755
> =====================================
>
>


-- 
=====================================
-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
=====================================