Re: Verilog-AMS Committee Meeting Minutes - Dec 22 2006

Geoffrey.Coram wrote:

>edaorg@v-ms.com wrote:
>  
>
>>Can you give an example of the issue with switch branches?
>>    
>>
>
>The issue here is something like:
>
>  electrical p,n;
>
>  analog begin : test1
>    I(p,n) <+ 5.0;
>  end
>
>  analog continue : test1
>    V(p,n) <+ 0.0;
>  end
>
>  analog continue : test1
>    I(p,n) <+ 3.0;
>  end
>
>When contributing to the current I, the switch branch is a
>"flow source" and the potential can vary; when contributing
>to V, it's a "potential source."  It gets slightly more
>complicated when one adds if() statements in each analog
>block, but the concept is the same.
>
>If these statements are in the same analog block, then the
>LRM already says that the last assignment wins, and also
>that when contributing the V, the 5A contrib to I is
>discarded, and then when contributing 3A, the V is 
>discarded (and the 5A stays discarded) -- if one removes
>the V-contrib, the two I contribs add (value retention).
>
>If these are in separate analog blocks, and we're not
>concatenating them, then it's hard to know whether one
>gets 0V, 3A, 5A, or 8A on that branch.
>  
>
But if they are not concatenated it doesn't matter if they are in the 
same module or seperate modules, you still have the same problem (i.e no 
ordering).

I would have said (with my EE hat on) that the obvious result of the 
above example is 0V across (p,n) and 8A through it, ordering is immaterial.

As I alluded to in the last e-mail you don't evaluate analog blocks by 
doing one pass through the code, there are multiple iterations and 
nothing is decided until it is all decided. The analog blocks are 
evaluated concurrently. It's just internally to a particular block that 
you have the "last assignment wins" since the block can only have one 
contribution to a branch (much the same as a digital process can only 
have one driver for a signal).

With my EE hat on again I would only see a problem if you have multiple 
contributions of voltage to (p,n) that are different, i.e. I can 
parallel up as many short-circuits or 1.5V supplies as I like, it'll 
only blow up if I have a short-circuit and 1.5V across (p,n).

So my vote goes to having it be a run-time fault to have multiple analog 
blocks having differing potential contributions to the same branch, 
although in degenerate cases (without switch branches and with constant 
potentials) you should be able to work out that there's a fault at 
elaboration.

Kev.

>-Geoffrey
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>