Re: Verilog-AMS Committee Meeting Minutes - Dec 22 2006

> edaorg@v-ms.com wrote:
> 
> Geoffrey.Coram wrote:
> 
> >   electrical p,n;
> >
> >   analog begin : test1
> >     I(p,n) <+ 5.0;
> >   end
> >
> >   analog continue : test1
> >     V(p,n) <+ 0.0;
> >   end
> >
> >   analog continue : test1
> >     I(p,n) <+ 3.0;
> >   end
[snip]
> But if they are not concatenated it doesn't matter if they are in the
> same module or seperate modules, you still have the same problem
> (i.e no ordering).

If they are in separate modules, then it's like you have two current
sources and a voltage source connected across the same two nodes.
The voltage is 0, and the v-source takes 8A plus whatever the rest
of the circuit contributes.

> I would have said (with my EE hat on) that the obvious result of the
> above example is 0V across (p,n) and 8A through it, ordering is immaterial.

If the analog blocks are concatenated to get
  analog begin
    I(p,n) <+ 5.0;
    V(p,n) <+ 0.0;
    I(p,n) <+ 3.0;
  end

then the result is 3A between p and n, with no constraint (from
this module) on the voltage.

-Geoffrey

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