RE: Verilog-AMS Committee Meeting Minutes - Dec 22 2006

Following SV's use of "unique" and "priority" as modifiers to "if" and
"case", e.g,. 

priority case(expr)

...

endcase

 

maybe you could just write "analog continue" or "continue analog".

 

Shalom

 

2) use "continue" instead of "begin" as the start of a continued analog
block. 

   analog 
     continue : active 
     end 

It is recognized that in both cases there is overlap with the "continue"
keyword in SV, but neither in a way that is incompatible with its use
there. It was agreed that the second way is syntactically cleaner. The
continued analog sequential block is restricted to the top-level in an
analog construct. This needs to be documented in section 6. 

While 2 might be neater, I don't think there is any other syntax where a
"end" is not matched with a "begin", so I'll
propose a third option: allow labeling the "analog" itself e.g.:

    analog : active
        begin 
            // some initial stuff
        end
   ...
   analog : continue active
        X <+ Y;  // a single statement
   ...
   analog : continue active
        begin 
            ... // multiple statements
        end