RE: multiple analog blocks

Dave,

1364-2005, 10.4.5 says,

"Constant functions are a subset of normal Verilog functions that shall
meet the following constraints:

- They shall contain no hierarchical references.
- Any function invoked within a constant function shall be a constant
function local to the current module.
- It shall be legal to call any system function that is allowed in a
constant_expression (see Clause 5). Calls to other system functions
shall be illegal.
- All system tasks within a constant function shall be ignored.
- All parameter values used within the function shall be defined before
the use of the invoking constant function call (i.e., any parameter use
in the evaluation of a constant function call constitutes a use of that
parameter at the site of the original constant function call).
- All identifiers that are not parameters or functions shall be declared
locally to the current function.
- If they use any parameter value that is affected directly or
indirectly by a defparam statement (see 12.2.1), the result is
undefined. This can produce an error or the constant function can return
an indeterminate value.
- They shall not be declared inside a generate block (see 12.4).
- They shall not themselves use constant functions in any context
requiring a constant expression."

Regards,
Shalom

> -----Original Message-----
> From: Dave Miller [mailto:David.L.Miller@freescale.com]
> Sent: Tuesday, December 26, 2006 4:01 PM
> To: Bresticker, Shalom
> Cc: verilog-ams
> Subject: Re: multiple analog blocks
> 
> Bresticker, Shalom wrote:
> > It's a little more complicated than that, but that's the general
idea.
> >
> > Shalom
> >
> >
> >> Any analog user defined function who's arguments are constant
> >> (parameters, numbers) is a constant function, as they can be solved
> >> pre-simulation with no dependencies on a matrix etc.
> >>
> >
> >
> Well in Verilog-AMS the difference between a constant UDF and a
> non-constant UDF is simply the input values being passed in. Is that
not
> the same in digital? Note, in Verilog-AMS you can't declare
> quantities/disciplines inside a UDF, only parameters and variables
> (ints, reals, that will be local to the UDF scope).
> 
> Dave
> 
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