Re: multiple analog blocks

From: Dave Miller <David.L.Miller_at_.....>
Date: Tue Dec 26 2006 - 06:00:41 PST
Bresticker, Shalom wrote:
> It's a little more complicated than that, but that's the general idea.
>
> Shalom
>
>   
>> Any analog user defined function who's arguments are constant
>> (parameters, numbers) is a constant function, as they can be solved
>> pre-simulation with no dependencies on a matrix etc.
>>     
>
>   
Well in Verilog-AMS the difference between a constant UDF and a 
non-constant UDF is simply the input values being passed in. Is that not 
the same in digital? Note, in Verilog-AMS you can't declare 
quantities/disciplines inside a UDF, only parameters and variables 
(ints, reals, that will be local to the UDF scope).

Dave

-- 
=====================================
-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
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Received on Tue Dec 26 06:00:47 2006

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