Verilog-AMS committee meeting agenda - 11 Jan 2006

Hi all,

Date & Time: 11 Jan 2006, 9-10pm Pacific

Call-In Details:
  USA Toll Free Number: 877-346-8823
  USA Toll Number: +1-203-320-0407 (for intl)
  Participant Passcode: 602538

The new call times are:

09:00 PM Pacific   (Thursday)
11:00 PM Central   (Thursday)
Midnight Eastern
06:00 AM Eindhoven (Friday)
10:30 AM India     (Friday)
03:30 AM Adelaide  (Friday)

Agenda:

   * Brief discussion on how to move forward on the multiple analog 
blocks proposal and chapter 7 review based on current discussions 
(covered in last meeting and through the reflector).

The following, if not a complete list, are some of the items that have 
been discussed.
     - continued sequential blocks using "continue" as used in SV
     - handling concurrency in analog blocks
     - initialization issues
     - Execution sequence of the analog blocks (and guarantee of results 
one executing single analog blocks vs multiple analog blocks)
     - Contribution to switch branches and the issue of named/unnamed 
braches
     - Handling of port connections and paramsets
     - Resolution of using hierarchical reference for nets: digital vs 
analog context for testbenches. Couple of proposals have been submitted 
using keyword vs casting syntax using in System Verilog

   * Simultaneously start working on Chapter 10 review. An initial 
proposal has been submitted and uploaded in the AMS webpage.


Regards,
Sri

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