Verilog-AMS LRM Committee Meeting - 4th Jan 2006

Hi all,

Date & Time: 4 Jan 2006, 9-10pm Pacific

Call-In Details:
  USA Toll Free Number: 877-346-8823
  USA Toll Number: +1-203-320-0407 (for intl)
  Participant Passcode: 602538

The new call times are:

09:00 PM Pacific   (Thursday)
11:00 PM Central   (Thursday)
Midnight Eastern
06:00 AM Eindhoven (Friday)
10:30 AM India     (Friday)
03:30 AM Adelaide  (Friday)

Agenda:

   * Multiple analog blocks proposal based on current discussions 
(covered in last meeting and through the reflector)
     - continued sequential blocks using "continue" as used in SV 
(discussed in last meeting)
     - handling concurrency in analog blocks
     - initialization issues
     - Execution sequence of the analog blocks (and guarantee of results 
one executing single analog blocks vs multiple analog blocks)
     - Contribution to switch branches (and the issue of named/unnamed 
braches)
     - Handling of port connections and paramsets

   * Resolution of using hierarchical reference for nets (digital vs 
analog context) for testbenches. Couple of proposals have been submitted 
(using specific keyword vs casting syntax using in System Verilog)
     - Not sure whether there has been a resolution on this and hence 
adding this to the agenda list.


cheers,
Sri
-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
Ph: +91-120-439 7021 F: x5199

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