All,
During work on the "Multiple Analog
Blocks" I ran across the following issue:
A 1364-2005 generate statement creates
a new scope. As a result, the concatenation of analog blocks needs to take
this into account, by adding this new scope into the concatenation. To
properly handle the referencing of variables in a named block it seems
to be necessary to implement the upward hierarchical references mentioned
in section 12.7 of the 1364-2005 as well. This should be part of Verilog-AMS
2.3 section 7.
Curiously, SystemVerilog (1800-2005)
does not mention generate statements at all. Is it still part of that standard
if it is only mentioned by 1364-2005? This is of particular interest to
the future Verilog-AMS 2.4 work.
Cheers,
Marq
Marq Kole
Competence Leader Robust Design
Research
NXP Semiconductors
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Received on Mon Jan 22 08:12:45 2007