RE: analog blocks and generate constructs

By the way, a subgroup of 1800's SV-BC is currently discussing upward
hierarchical references, as the descriptions in both 1364-2005 12.5-12.7
and 1800-2005 19.3 are not complete and not completely accurate.

 

Shalom

 

A 1364-2005 generate statement creates a new scope. As a result, the
concatenation of analog blocks needs to take this into account, by
adding this new scope into the concatenation. To properly handle the
referencing of variables in a named block it seems to be necessary to
implement the upward hierarchical references mentioned in section 12.7
of the 1364-2005 as well. This should be part of Verilog-AMS 2.3 section
7. 




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