A/D instance path [was Re: analog blocks and generate constructs]

That reminds me - it's not very clear what the path of an auto-inserted 
connect module instance is. Section 8.8.5 seems to define names but not 
paths.

The reason that it's important is that you want to be able to do an 
upward hierarchical reference from the A/D connect module to find power 
supplies etc. If you back-annotate a design then you are probably going 
to insert stuff between the ports so you want the A/D to be a child of 
the module where the driver, contribution or receiver is.

Note: if the auto-inserted instance is a child of the module for which 
the conversion is required it's name doesn't need to include the parent 
module name. Also, for the 8.8.5 "merged" it is not clear which 
discipline is being used in the name - and if it is the resolved 
discipline the instance path will be a bit unpredictable.

If folks agree I'll do a quick rewrite of 8.8.5.

Kev.



Bresticker, Shalom wrote:
>
> By the way, a subgroup of 1800’s SV-BC is currently discussing upward 
> hierarchical references, as the descriptions in both 1364-2005 
> 12.5-12.7 and 1800-2005 19.3 are not complete and not completely accurate.
>
> Shalom
>
> A 1364-2005 generate statement creates a new scope. As a result, the 
> concatenation of analog blocks needs to take this into account, by 
> adding this new scope into the concatenation. To properly handle the 
> referencing of variables in a named block it seems to be necessary to 
> implement the upward hierarchical references mentioned in section 12.7 
> of the 1364-2005 as well. This should be part of Verilog-AMS 2.3 
> section 7.
>
>
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