Jonathan David wrote: > I dnt hv cpy of sv spec...but only vlogA has idea of pct codes for fopen..its a little less useful for > opening files for read or append. might be better to support string operations (cat) on string variables and allow some pct codes there. > jonathan @ Isscc > I think someone brought up the issue of strings being declared as "reg" type in Verilog so if you wanted to make the file name programmable in Verilog-AMS you would run into the issue of defining how the reg was going to work in an analog context. If you add the plug expansion as an option to $fopen then you don't need to declare the variables for the string operations, so there is less extra work to do in the LRM (and for the user). An extra option you might want to consider is environment expansion so that you can do something like: $fopen ("$USER.$TEST.%a.%#","epw"); // e => expand environment, p => expand plugs(%) - file = kev.pll.dc.0 Kev. > --- owner-verilog-ams@eda.org <kevin@sonicsinc.com> > wrote: > >> Geoffrey.Coram wrote: >> >>> Martin O'Leary wrote: >>> >>> >>>> * Add percentage codes for analysis that can be used to uniquely name a file generated by an analysis. >>>> It a file is not uniquely name, it will be overwritten if there are multiple analysis opening, closing and writing to the file. >>>> >>> Let's be sure that SV is going to go along with this; there are only 26 percent codes, and most of them are already used. We don't want SV to assign a different meaning. >>> >> Actually there are lots more than 26 since you could use uppercase and they don't have to be single character or just a-z. >> >>> What does this code look like? If I put "results_%a" do I get files like "results_dc" "results_ac" ... >>> >>> Or are the names more like the temporary filenames generated by the C function "tmpnam"? >>> >>> On one hand, it would be nice to know that dc results are in "results_dc"; on the other, I don't want the results of the second dc analysis in a single netlist to overwrite those of the first dc analysis. >>> >>> >> Maybe we could add (say) %A to indicated the run number e.g. >> >> "results_%a.%A" would be " >> >> "results_dc.0","results_dc.1",... >> >> Alternatively add extra modes for to $fopen for no-clobber/versions, e.g.: >> >> $fopen(results,"wv"); // v => new version (add .<number> automatically). >> >> or tell fopen to do a plug expansion on the file name e.g.: >> >> $fopen("results_%a.%A","we",...); // e => expand plugs in filename. >> >> - that saves having to create your own strings. >> >> Kev. >> >> >>> Some simulators have names for the analysis, eg "dc1" in this: >>> >>> dc1 dc start=0 stop=5 >>> Will the percent code use this name? On one hand, this would give good control to the user; on the other hand, it may be inappropriate to dictate this for the simulator in an HDL manual. >>> >>> -Geoffrey >>> >>> >>> Codes used in Verilog 1364-2005: >>> b,c,d,e,f,g,h, ,l,m, ,o, ,s,t,u,v, ,z >>> >>> C uses i,n,p,x in some implementations, though % looks to the same as %d; %x is "unsigned hex" in C, whereas %h is "hex" in Verilog. Also, %u is "unsigned decimal" in C, but "unformatted 2-value" in Verilog. (%p is for a pointer. %n is strange: printf outputs nothing but instead stores back into the corresponding argument the number of characters printed so far.) >>> >>> I don't see any new ones in 1800-2005. AMS uses %r. >>> >>> That leaves: a,j,k,q,w,y %a sure would be nice for analysis ... >>> > > > Jonathan David > j.david@ieee.org > jb_david@yahoo.com > http://ieee-jbdavid.blogspot.com > Mobile 408 390 2425 > Work: > jbdavid@scintera.com > http://www.scintera.com > 408 636-2618 > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Feb 12 12:19:48 2007
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