RE: percent codes for analyses (was: Feb 8 2007 minutes)

From: Martin O'Leary <oleary_at_.....>
Date: Mon Feb 12 2007 - 12:46:25 PST
Geoffrey, Kevin, Jonathan
thanks for your input.
Comments below.
--Martin 

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Geoffrey.Coram
Sent: Monday, February 12, 2007 4:52 AM
Cc: verilog-ams
Subject: percent codes for analyses (was: Feb 8 2007 minutes)

Martin O'Leary wrote:
> 
> * Add percentage codes for analysis that can be used to uniquely name 
> a file generated by an analysis.
> It a file is not uniquely name, it will be overwritten if there are 
> multiple analysis opening, closing and writing to the file.

Let's be sure that SV is going to go along with this; there are only 26
percent codes, and most of them are already used.  We don't want SV to
assign a different meaning.

What does this code look like?  If I put "results_%a" to I get files
like "results_dc" "results_ac" ...

oleary>My take that we should use multiple character percentage codes in
order to avoid conflict with the SV standard or reserving too much of
the name space. They would all start with '%a' or '%A' - a/A for AMS.
e.g. %aa for analysis, %as for simulator name, etc ...
As suggested %a and %r would then need to be reserved for use by
Verilog-AMS only.
This I hope would address 
1) the risk of SV and Verilog-AMS coming into conflict
2) allow a mechanism for the Verilog-AMS to expand the percentage code
capabilities easily
3) consumming too much of percentage code name space.


Or are the names more like the temporary filenames generated by the C
function "tmpnam"?

On one hand, it would be nice to know that dc results are in
"results_dc"; on the other, I don't want the results of the second dc
analysis in a single netlist to overwrite those of the first dc
analysis.

Some simulators have names for the analysis, eg "dc1" in this:
dc1 dc start=0 stop=5
Will the percent code use this name?  On one hand, this would give good
control to the user; on the other hand, it may be inappropriate to
dictate this for the simulator in an HDL manual.

oleary>The file would be named after the analysis name (ie. dc1 ) not
the analysis type (dc).
I believe many simulators already have some kind of analysis
naming/tagging scheme if only to determine the name of the different
transient output waveform files when multiple transient analyses are
being conducted.

-Geoffrey


Codes used in Verilog 1364-2005:
b,c,d,e,f,g,h, ,l,m, ,o, ,s,t,u,v, ,z

C uses i,n,p,x in some implementations, though %i looks to the same as
%d; %x is "unsigned hex" in C, whereas %h is "hex" in Verilog.  Also, %u
is "unsigned decimal"
in C, but "unformatted 2-value" in Verilog.  (%p is for a pointer. %n is
strange: printf outputs nothing but instead stores back into the
corresponding argument the number of characters printed so far.)

I don't see any new ones in 1800-2005.  AMS uses %r.

That leaves: a,j,k,q,w,y  %a sure would be nice for analysis ...

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Received on Mon Feb 12 12:46:55 2007

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