Strings is my vote if we had to incorporate anything into Verilog-A. Definitely not registers. But I wonder if we might want to hold off on adding a new data type for this revision, else it may drag on forever. Dave Martin O'Leary wrote: > David, > I hope we can discuss this point at the meeting on Thursday. > > The dilemma is that the strings functionality would be useful in analog > (as is event by the recent threads) but that to make them work in analog > the Verilog-AMS LRM need to either supports regs (from V2005) or strings > (from SV) in the analog context. > > Thanks, > --Martin > > -----Original Message----- > From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On > Behalf Of David Miller > Sent: Tuesday, February 13, 2007 6:43 AM > To: Verilog-AMS LRM Committee > Subject: Section 10: $swrite and $sformat > > In the latest revision document we have $swrite and $sformat as being > supported in both digital and analog. > I think these should be only supported in digital since we have no > string data type that we can write to during simulation (and we are not > going to support assigning of registers in analog. > > Unless we want to add in a new data type "string" that can be assigned > during behaviour. > > Dave > > -- > This message has been scanned for viruses and dangerous content by > MailScanner, and is believed to be clean. > > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Feb 13 15:17:08 2007
This archive was generated by hypermail 2.1.8 : Tue Feb 13 2007 - 15:17:10 PST