Re: Section 10: $swrite and $sformat

I would have thought 'reg' would be better since it's common to both.

What's the problem with allowing reg types anyway?

- regs declared in routines don't work the same way as regs in modules, 
so in a similar vein you could just limit the semantics of a reg 
declared in an analog block to what you need for the string handling.

Kev.


David Miller wrote:
> Strings is my vote if we had to incorporate anything into Verilog-A. 
> Definitely not registers.
> But I wonder if we might want to hold off on adding a new data type 
> for this revision, else it may drag on forever.
>
> Dave
>
> Martin O'Leary wrote:
>> David,
>> I hope we can discuss this point at the meeting on Thursday.
>>
>> The dilemma is that the strings functionality would be useful in analog
>> (as is event by the recent threads) but that to make them work in analog
>> the Verilog-AMS LRM need to either supports regs (from V2005) or strings
>> (from SV) in the analog context.
>>
>> Thanks,
>> --Martin
>>
>> -----Original Message-----
>> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
>> Behalf Of David Miller
>> Sent: Tuesday, February 13, 2007 6:43 AM
>> To: Verilog-AMS LRM Committee
>> Subject: Section 10: $swrite and $sformat
>>
>> In the latest revision document we have $swrite and $sformat as being
>> supported in both digital and analog.
>> I think these should be only supported in digital since we have no
>> string data type that we can write to during simulation (and we are not
>> going to support assigning of registers in analog.
>>
>> Unless we want to add in a new data type "string" that can be assigned
>> during behaviour.
>>
>> Dave
>>
>> -- 
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>>
>>   
>
>


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