Re: error in NAND example

Geoffrey.Coram wrote:
> Someone at Designers-Guide.org was using the NAND
> example from the Verilog-AMS web site:
>   http://www.eda.org/verilog-ams/models/nand.va
>
> I'm not familiar with the generate statement,
> but it sure looks to me that the generate uses
> the same variable (i) that the second 
> for-loop uses.
>
> The same problem is in the nor.va model.
>
> -Geoffrey
>
>   
Yes that model is incorrect. Not only is same genvar i used for both the 
top level generate loop and the lower level analog for loop, it is never 
declared. I can't find genvar i anywhere?

Dave


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