Re: error in NAND example

Geoffrey and all,

Upon inspection the ideal_adc.va model also has this missing genvar 
declaration and would therefore not compile with a modern compiler 
implementation. What is exactly the status of these models and how long 
have they been around? Is any maintenance planned for these models or are 
they a one-time selection of examples against one particluar version of 
the LRM?

Sorry, just a bunch of questions, but these models are not in our 
advantage if they are not proper Verilog-AMS but appear on the website of 
the standardization committee...

Cheers,
Marq


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors









"Geoffrey.Coram" <Geoffrey.Coram@analog.com> 
Sent by:
owner-verilog-ams@server.eda.org
02-03-2007 21:04

To
VerilogAMS Reflector <verilog-ams@server.eda.org>
cc

Subject
error in NAND example
Classification







Someone at Designers-Guide.org was using the NAND
example from the Verilog-AMS web site:
  http://www.eda.org/verilog-ams/models/nand.va

I'm not familiar with the generate statement,
but it sure looks to me that the generate uses
the same variable (i) that the second 
for-loop uses.

The same problem is in the nor.va model.

-Geoffrey

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