These models have been around for a very long time; the timestamps say 1998, which means Verilog-A 1.0. I'd be happy to help re-write a few, if someone else wants to write a testbench to verify they work. -Geoffrey Marq Kole wrote: > > Geoffrey and all, > > Upon inspection the ideal_adc.va model also has this missing genvar declaration and would therefore not compile with a modern compiler implementation. What is exactly the status of these models and how long have they been around? Is any maintenance planned for these models or are they a one-time selection of examples against one particluar version of the LRM? > > Sorry, just a bunch of questions, but these models are not in our advantage if they are not proper Verilog-AMS but appear on the website of the standardization committee... > > Cheers, > Marq -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Mar 5 06:14:59 2007
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