Laurent,
Here it is:
wget -r -l 1 --no-host-directories \
http://www.eda-stds.org/verilog-ams/htmlpages/sample_lib.bedm.html
\
http://www.eda-stds.org/verilog-ams/htmlpages/sample_lib.sdm.html
\
http://www.eda-stds.org/verilog-ams/htmlpages/sample_lib.bfem.html
\
http://www.eda-stds.org/verilog-ams/htmlpages/sample_lib.afem.html
\
http://www.eda-stds.org/verilog-ams/htmlpages/sample_lib.dcm.html
\
http://www.eda-stds.org/verilog-ams/htmlpages/sample_lib.maem.html
\
http://www.eda-stds.org/verilog-ams/htmlpages/sample_lib.adcm.html
\
http://www.eda-stds.org/verilog-ams/htmlpages/sample_lib.matm.html
This will give you a directory "verilog-ams"
in the current path with all examples in the subdirectory "models"
of that directory.
By the way, I've already started updating
(at 70% now), so I can send out a tar file with updated examples that at
least compile fine with a commercial Verilog-A compiler we're using. Test
becnhes to be able to verify correct behaviour of the models may then follow
later.
Cheers,
Marq
Marq Kole
Competence Leader Robust Design
Research
NXP Semiconductors
"Lemaitre Laurent-r29173"
<Laurent.Lemaitre@freescale.com>
06-03-2007 11:22
|
|
To
| "Marq Kole" <marq.kole@nxp.com>
|
|
cc
|
|
|
Subject
| RE: error in NAND example
|
|
Classification
| |
|
Hi Mark,
I tried to get the examples with
wget with different options.
But I can't just get the .va files.
Can you send me the wget args
you used?
Thanks,
Laurent
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org]
On Behalf Of Marq Kole
Sent: Tuesday, March 06, 2007 10:50 AM
To: verilog-ams@eda-stds.org
Subject: Re: error in NAND example
Geoffrey,
I can construct some test benches; can I assume spectre format is OK?
I just retrieved all examples (viva wget!), and ran a 2.2 compliant compiler
on the Verilog-A itself. Of the 146 examples, 72 generated errors (plus
6 warnings). Most of these warnings are quite trivial, either undefined
macro's or disciplines (no includes), some of them related to the examples
actually being Verilog-AMS, a few related to compiler limitations. Most
of them are portability issues between Verilog-AMS 1.0 and Verilog-AMS
2.2.
There is one erroneous link in the page http://www.eda-stds.org/verilog-ams/htmlpages/sample_lib.afem.html:
the file V_ctrl_pwl_limited.va cannot be found. Can you check whether there
is a file present in the directory with a similar name or is it completely
absent?
Cheers,
Marq
Marq Kole
Competence Leader Robust Design
Research
NXP Semiconductors
"Geoffrey.Coram" <Geoffrey.Coram@analog.com>
Sent by:
geoffrey.coram@analog.com
05-03-2007 15:14
|
|
To
| Marq Kole <marq.kole@nxp.com>
|
|
cc
| verilog-ams@eda-stds.org
|
|
Subject
| Re: error in NAND example
|
|
Classification
| |
|
These models have been around for a very long time; the timestamps
say 1998, which means Verilog-A 1.0.
I'd be happy to help re-write a few, if someone else wants to
write a testbench to verify they work.
-Geoffrey
Marq Kole wrote:
>
> Geoffrey and all,
>
> Upon inspection the ideal_adc.va model also has this missing genvar
declaration and would therefore not compile with a modern compiler implementation.
What is exactly the status of these models and how long have they been
around? Is any maintenance planned for these models or are they a one-time
selection of examples against one particluar version of the LRM?
>
> Sorry, just a bunch of questions, but these models are not in our
advantage if they are not proper Verilog-AMS but appear on the website
of the standardization committee...
>
> Cheers,
> Marq
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Received on Tue Mar 6 02:49:51 2007