Sri, Geoffrey,
I've made updates to the Verilog-A models
from the Examples section and for testing purposes compiled them with two
different available compilers. The only remaining issues with the models
are errors on unsupported features in either or both of these compilers
and any additional errors hidden behind the "unsupported feature"
errors. The unsupported features themselves are Verilog-AMS LRM 2.2 compliant,
it's just that the compilers can't handle these yet. As such a nice test
set for those who want to verify their compilers.
The test benches are still an open item;
I intend to create a couple, based on simple time-domain tests so they
can be run in either circuit simulators as well as AMS simulators. I presume
that for the Verilog-AMS standardization site, we do not want to have a
bias towards a particular simulator, so I'm considering writing the test
benches in Verilog-AMS itself.
Instead of sending everyone on this
mailing list a copy of the models, should we just update the existing models
on the site - which we "know" are buggy - or do we want a quality
check first? The simplest check is to make an empty netlist file that just
loads (and compiles) the Verilog-A(MS) files. More elaborate tests really
would ask for a test bench. What's your opinion?
Cheers,
Marq
Marq Kole
Competence Leader Robust Design
Research
NXP Semiconductors
Marq Kole <marq.kole@nxp.com>
Sent by:
owner-verilog-ams@server.eda.org
06-03-2007 10:49
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To
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cc
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Subject
| Re: error in NAND example
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Classification
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Geoffrey,
I can construct some test benches; can I assume spectre format is OK?
I just retrieved all examples (viva wget!), and ran a 2.2 compliant compiler
on the Verilog-A itself. Of the 146 examples, 72 generated errors (plus
6 warnings). Most of these warnings are quite trivial, either undefined
macro's or disciplines (no includes), some of them related to the examples
actually being Verilog-AMS, a few related to compiler limitations. Most
of them are portability issues between Verilog-AMS 1.0 and Verilog-AMS
2.2.
There is one erroneous link in the page http://www.eda-stds.org/verilog-ams/htmlpages/sample_lib.afem.html:
the file V_ctrl_pwl_limited.va cannot be found. Can you check whether there
is a file present in the directory with a similar name or is it completely
absent?
Cheers,
Marq
Marq Kole
Competence Leader Robust Design
Research
NXP Semiconductors
"Geoffrey.Coram" <Geoffrey.Coram@analog.com>
Sent by:
geoffrey.coram@analog.com
05-03-2007 15:14
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To
| Marq Kole <marq.kole@nxp.com>
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cc
| verilog-ams@eda-stds.org
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Subject
| Re: error in NAND example
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Classification
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These models have been around for a very long time; the timestamps
say 1998, which means Verilog-A 1.0.
I'd be happy to help re-write a few, if someone else wants to
write a testbench to verify they work.
-Geoffrey
Marq Kole wrote:
>
> Geoffrey and all,
>
> Upon inspection the ideal_adc.va model also has this missing genvar
declaration and would therefore not compile with a modern compiler implementation.
What is exactly the status of these models and how long have they been
around? Is any maintenance planned for these models or are they a one-time
selection of examples against one particluar version of the LRM?
>
> Sorry, just a bunch of questions, but these models are not in our
advantage if they are not proper Verilog-AMS but appear on the website
of the standardization committee...
>
> Cheers,
> Marq
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Received on Tue Mar 6 06:58:38 2007