Verilog-A examples

Geoffrey,
     about a year ago I organized an effort within Synopsys to take the
models in the LRM, fix them, and add testbenches for HSPICE. The result
is available to Synopsys customers at HSPICE.com, Download Verilog-A
models.
Please do not be deterred by the license agreement which comes up. In my
humble opinion we should be able to work something out to allow for
general
distribution of these models through Accellera, for the sake of
promoting
Verilog-A. Let me know if you are interested. 
Regards
	Oskar

----------------------------------------------------------------------
Oskar Leuthold, Corporate Applications Engineer
Analog Mixed Signal Group
Synopsys, Inc.  700 E. Middlefield Rd.
Mountain View, CA 94043
650 584 5887    oskar.leuthold@synopsys.com


 

> -----Original Message-----
> From: owner-verilog-ams@eda.org 
> [mailto:owner-verilog-ams@eda.org] On Behalf Of Geoffrey.Coram
> Sent: Tuesday, March 06, 2007 7:09 AM
> To: Marq Kole
> Cc: verilog-ams
> Subject: Re: error in NAND example
> 
> Marq -
> I really like the designers-guide.org approach of having a 
> netlist for each model.  However, I think we should go ahead 
> and upload the revised models even without the testbench.
> 
> -Geoffrey
> 
> 
> Marq Kole wrote:
> > 
> > Sri, Geoffrey,
> > 
> > I've made updates to the Verilog-A models from the Examples 
> section and for testing purposes compiled them with two 
> different available compilers. The only remaining issues with 
> the models are errors on unsupported features in either or 
> both of these compilers and any additional errors hidden 
> behind the "unsupported feature" errors. The unsupported 
> features themselves are Verilog-AMS LRM 2.2 compliant, it's 
> just that the compilers can't handle these yet. As such a 
> nice test set for those who want to verify their compilers.
> > 
> > The test benches are still an open item; I intend to create 
> a couple, based on simple time-domain tests so they can be 
> run in either circuit simulators as well as AMS simulators. I 
> presume that for the Verilog-AMS standardization site, we do 
> not want to have a bias towards a particular simulator, so 
> I'm considering writing the test benches in Verilog-AMS itself.
> > 
> > Instead of sending everyone on this mailing list a copy of 
> the models, should we just update the existing models on the 
> site - which we "know" are buggy - or do we want a quality 
> check first? The simplest check is to make an empty netlist 
> file that just loads (and compiles) the Verilog-A(MS) files. 
> More elaborate tests really would ask for a test bench. 
> What's your opinion?
> > 
> > Cheers,
> > Marq
> 
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