Re: Verilog-AMS Committee Meeting Minutes - Mar 1st 2007

I don't think anything needs to be changed in this section. Any module 
level variables are output variables, so string variables will be 
automatically included.

Dave

Marq Kole wrote:
>
> All,
>
> > * Martin to talk to Geoffrey about reworking Chapter 3 to support
> > strings variables
>
> Just an idea, but should string variables also be supported as output 
> variables, i.e. should section 3.1.1 be extended with string output 
> variables as well?
>
> Cheers,
> Marq
>
>
> Marq Kole
> Competence Leader Robust Design
>
> Research
> NXP Semiconductors
>
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