Re: Verilog-AMS Committee Meeting Minutes - Mar 1st 2007

From: Marq Kole <marq.kole_at_.....>
Date: Thu Mar 15 2007 - 07:07:39 PDT

David,

That's only true if they have been annotated with a "desc" and "units" attribute. However, as that behaviour is optional it indeed isn't much of an issue. Still, the output variables is now specifically mentioned as a subsection of the integer and real datatypes. If string variables can also be output variables that indicates that string variables should be described as part of section 3.1.

Cheers,
Marq


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors

David Miller <David.L.Miller@freescale.com> Sent by: owner-verilog-ams@server.eda.org 15-03-2007 13:46

To Marq Kole <marq.kole@nxp.com> cc verilog-ams <verilog-ams@server.eda-stds.org> Subject Re: Verilog-AMS Committee Meeting Minutes - Mar 1st 2007 Classification

I don't think anything needs to be changed in this section. Any module
level variables are output variables, so string variables will be
automatically included.

Dave

Marq Kole wrote:
>
> All,
>
> > * Martin to talk to Geoffrey about reworking Chapter 3 to support
> > strings variables
>
> Just an idea, but should string variables also be supported as output
> variables, i.e. should section 3.1.1 be extended with string output
> variables as well?
>
> Cheers,
> Marq
>
>
> Marq Kole
> Competence Leader Robust Design
>
> Research
> NXP Semiconductors
>
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